DATASHEET
LOW EMI CLOCK GENERATOR
Description
The MK1707 generates a low EMI output clock from a clock
input. The part is designed to dither the LCD interface clock
for flat panel graphics controllers. The device uses IDT’
proprietary mix of analog and digital Phase Locked Loop
(PLL) technology to spread the frequency spectrum of the
output, thereby reducing the frequency amplitude peaks by
several dB.
The MK1707 offers both centered and down spread from a
high speed clock input. Refer to the MK1714-01/02 for a
crystal input and the widest selection of input frequencies
and multipliers.
IDT offers many other clocks for computers and computer
peripherals. Consult us when you need to remove crystals
and oscillators from your board.
MK1707
Features
•
•
•
•
•
•
•
Packaged in 8-pin SOIC
Available in Pb-free package
Industrial temperature range available
Provides a spread spectrum output clock
Supports ATI’s flat panel controllers
Guaranteed to +85° C operation
Accepts a clock input, provides same frequency dithered
output
•
Good for all VGA modes from 80 to 167 MHz
•
Peak reduction by 7dB - 14dB typical on 3rd - 19th odd
harmonics
•
•
•
•
Low EMI feature can be disabled
Includes Power-down
Operating voltage of 3.3 V or 5 V
Advanced, low-power CMOS process
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD
S1:0
Spread Direction
Low EMI Enable
2
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
Input
Buffer
Clock Out
ICLK
GND
IDT™
LOW EMI CLOCK GENERATOR
1
MK1707
REV H 121809
MK1707
LOW EMI CLOCK GENERATOR
SSCG
External Components
The MK1707 requires a minimum number of external
components for proper operation.
Powerup Considerations
To insure proper operation of the spread spectrum
generation circuit, some precautions must be taken while
utilizing the MK1707.
1. An input signal should not be applied to ICLK until VDD is
stable (within 10% of its final value). This requirement can
easily be met by operating the MK1707 and then ICLK
source from the same power supply.
2. LEE should not be enabled (taken high) until after the
power supplies and input clock are stable. This requirement
can be met by direct control of LEE by system logic - for
example, a “power good” signal. Another solution is to leave
LEE unconnected to anything but a 0.01
µ
F capacitor to
ground. The internal pullup resistor on LEE will charge the
capacitor and provide approximately a 700
µ
s delay until
spread spectrum is enabled.
3. If the input frequency is changed during operation,
disable spread spectrum until the input clock stabilizes at
the new frequency.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3, as close to these
pins as possible. For optimum device performance, the
decoupling capacitor should be mounted on the component
side of the PCB. Avoid the use of vias in the decoupling
circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50
Ω
trace (a commonly used trace impedance),
place a 33
Ω
resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20
Ω
.
Tri-level Select Pin Operation
The S1, S0 select pins are tri-level, meaning they have three
separate states to make the selections shown in the table on
page 2. To select the M (mid) level, the connection to these
pins must be eliminated by either floating them originally, or
tri-stating the GPIO pins which drive the select pins.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) To minimize EMI, the 33
Ω
series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK1707. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
IDT™
LOW EMI CLOCK GENERATOR
3
MK1707
REV H 121809
MK1707
LOW EMI CLOCK GENERATOR
SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1707. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +85
°
C
-40 to +85
°
C
-65 to +150
°
C
125
°
C
260
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.135
Typ.
Max.
+85
+5.5
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V
, Ambient Temperature 0 to +85
°
C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
IDD
IDD
IDDPD
Conditions
No load, at 3.3 V
No load, at 5 V
S0=S1=SD=1
ICLK
ICLK
S1, S0
other inputs
S0, S1, SD, LEE pins
CMOS, I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= -12 mA
S0, S1, SD, LEE pins
Min.
3.135
Typ.
20
31
60
Max.
5.5
Units
V
mA
mA
µ
A
Input High Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
V
IH
V
IL
V
IH
V
IH
V
IL
V
OH
V
OH
V
OL
C
IN
(VDD/2) + 1
VDD-0.5
2
VDD/2
VDD/2
(VDD/2) - 1
V
V
V
V
0.5
V
V
V
0.4
V
pF
VDD-0.4
2.4
5
IDT™
LOW EMI CLOCK GENERATOR
4
MK1707
REV H 121809
stm32/stm8
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