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Vishay Sfernice
High Frequency 50 GHz Thin Film Chip Resistor
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Operating frequency 50 GHz
Thin film microwave resistors
Flip chip, wraparound or one face termination
Small size, down to 20 mils by 16 mils
Edged trimmed block resistors
Pure alumina substrate (99.5 %)
Ohmic range: 10R to 500R
Design kits available
Small internal reactance (LC down to 1 × 10
-24
)
Tolerance 1 %, 2 %, 5 %, 10 %
TCR: 100 ppm/°C in (-55 °C, +155 °C) temperature range
TCR: 50 ppm/°C available upon request for 10
to150
ohmic range
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
DESIGN SUPPORT TOOLS
Models
Available
click logo to get started
Those miniaturized components are designed in such a way
that their internal reactance is very small. When correctly
mounted and utilized, they function as almost pure resistors
on a very large range of frequency, up to 50 GHz.
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
CH02016
CH0402
CH0603
SIZE
02016
0402
0603
RESISTANCE
RANGE
10 to 500
10 to 500
10 to 500
RATED POWER
Pn
W
0.030
0.050
0.125
LIMITING ELEMENT
TOLERANCE
VOLTAGE
±%
V
30
2, 5, 10
37
1, 2, 5, 10
50
1. 2, 5, 10
TEMPERATURE
COEFFICIENT
± ppm/°C
100 (50 upon request)
100 (50 upon request)
100 (50 upon request)
DIMENSIONS
in millimeters (inches)
CH02016 F / CH02016 P /
CH0402 P / CH0603 P
CH0402 F / CH0603 F
CH0402 N / CH0402 G /
CH0603 N / CH0603 G
CASE SIZE
MODEL /
TERMINATION
CH02016 F
CH02016 P
CH0402 F
CH0402 N
CH0402 G
CH0402 P
CH0603 F
CH0603 N
CH0603 G
CH0603 P
Note
(1)
± 0.070 (± 0.003)
DIMENSIONS
A
± 0.10 (± 0.004)
0.480 (0.020)
1.000 (0.040)
1.200 (0.047)
1.520 (0.060)
1.720 (0.068)
B
± 0.10 (± 0.004)
0.390 (0.016)
0.600 (0.023)
0.600 (0.023)
0.750 (0.030)
0.750 (0.030)
D
C
F
E when applicable
± 0.127 (± 0.005)
± 0.050 (± 0.002)
MIN.
MAX.
0.110
0.150
0.260 (0.010)
0.420 (0.016)
(1)
(0.004)
(0.006)
0.500 (0.020)
0.500 (0.020)
0.500 (0.020)
0.500 (0.020)
0.150
(0.006)
0.110
(0.004)
0.250
(0.010)
0.235
(0.009)
0.350
(0.014)
0.150
(0.006)
0.510
(0.020)
0.275
(0.011)
n/a
0.320 (0.013)
n/a
0.660 (0.026)
G
± 0.050 (± 0.002)
0.300 (0.012)
n/a
0.880 (0.035)
n/a
1.355 (0.053)
Revision: 08-Feb-2019
Document Number: 53014
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
Vishay Sfernice
10
R
< 50
5 %, 10 %
50
R
< 100
2 %, 5 %, 10 %
100
R
500
1 %, 2 %, 5 %, 10 %
(1)
TOLERANCE VS. OHMIC VALUES
Ohmic range
Tolerance
Note
(1)
1 % tolerance not applicable for case 02016
LAND PATTERN FOR F 'FLIP CHIP' TERMINATIONS
in millimeters (inches)
G
min.
X
max.
Z
max.
CHIP SIZE
02016
0402
0603
Z
max.
0.53 (0.021)
1.40 (0.055)
1.71 (0.067)
X
max.
0.44 (0.017)
0.65 (0.026)
0.90 (0.035)
G
min.
0.15 (0.006)
0.40 (0.016)
0.76 (0.030)
Note
• Suggested land pattern: According to IPC-7351
LAND PATTERN FOR N AND G WRAPAROUND TERMINATIONS
in millimeters (inches)
G
min.
Z
max.
CHIP SIZE
0402
0603
Z
max.
1.55 (0.061)
2.37 (0.093)
G
min.
0.15 (0.006)
0.35 (0.014)
X
m
ax
.
X
max.
0.73 (0.029)
0.98 (0.039)
Dimension and tolerance of land pattern shall be defined by PCB designer; PCB can be designed according to IPC-7351A
“Generic Requirements for Surface Mount Design and Land Pattern Standard”
Revision: 08-Feb-2019
Document Number: 53014
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
PREFERRED MODELS AND VALUES
Vishay Sfernice highly recommend to use the smallest sizes and flip chip version to get the best performances.
Recommended Values:
10R/18R/25R/50R/75R/100R/150R/180R/200R/250R/330R/500R
Those values are available with a
MOQ of 100 pieces.
Other values can be ordered upon request, but higher MOQ will apply: 1000 pieces for CH02016, 500 pieces for CH0402,
50 pieces for CH0603.
Recommended termination:
F
Recommended tolerance:
2%
Vishay Sfernice
DESIGN KITS
Design kits are available Ex Stock in CH02016 and CH0402 sizes. There are 20 pieces per recommended value. F termination.
5 % tolerance.
Those kits are packaged in pieces of tape and delivered in ESD bags.
PACKAGING
Standard packaging is plastic tape and reel for all sizes.
Paper tape and reel is available for sizes 0402 and 0603.
Waffle pack is available for all sizes.
Depending on the type of terminations, parts will be packed differently:
One face:
• Gold terminations:
• Tin / silver terminations:
(P termination option):
(F termination option):
active face up
active face down in tape and reel
active face up in waffle pack
Note
• Please refer to Vishay Sfernice Application Note “Guidelines for Vishay Sfernice Resistive and Inductive Products” for soldering
recommendation (document number 52029, 3. Guidelines for Surface Mounting Components (SMD), profile number 3 applies
NUMBER OF PIECES PER PACKAGE
SIZE
MOQ
WAFFLE PACK
2" X 2"
484
100
100
100
5000
8 mm
TAPE AND REEL
Min.
Max.
TAPE WIDTH
02016
0402
0603
See MOQ mentioned
on preferred models
and values
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover. To get
“not stacked up” waffle pack in case of ordered quantity
> maximum number of pieces per package: Please consult
Vishay Sfernice for specific ordering code.
Tape and Reel
See Part Numbering information to get the quantity desired
by tape.
In regard to the CH02016 size only, up to 5 empty cavities
can be found every 1000 parts in the reel. Nevertheless, the
number of requested parts will be respected.
Revision: 08-Feb-2019
Document Number: 53014
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
Vishay Sfernice
GLOBAL PART NUMBER INFORMATION
New Global Part Numbering: CH0402-50RJF (preferred part number format)
C
H
0
4
SIZE
02016
0402
0603
0
2
-
5
TOLERANCE
F
=1%
G
=2%
J
=5%
K
= 10 %
0
R
J
F
T
PACKAGING
9
9
9
GLOBAL MODEL
CH
OHMIC VALUE
10R to 500R
TERMINATION
F
(Flip Chip):
SnAg over nickel barrier
N
(W/A):
SnAg over nickel barrier
(except 02016)
P
(one face):
(1)
Gold bonding pads
G
(W/A): Gold over
nickel barrier
(except 02016)
OPTION
From
1 to 3 digits.
Leave blank
if no option.
For more
information see
Codification of
Packaging table
Historical Part Number example: CH02016-100RGFPT1K (tapes of 1K pieces)
CH0402-50RJF
(waffle pack)
CHKIT Part Numbers
(2)
:
CHKIT-02016
CHKIT-0402
Notes
• Historical part numbers are not recommended but can still be used for ordering
(1)
Gold termination for application in hermetic package. Can also be mounted on PCB with SnAg solder paste
(2)
CHKIT for 0603 size is not available
CODIFICATION OF PACKAGING
WAFFLE PACK (available for all sizes)
W
PLASTIC TAPE (standard packaging for all sizes)
T
TA
TB
TC
TD
TE
TF
PAPER TAPE (available for 0402 and 0603)
PT
PA
PB
PC
PD (not available for size 0402)
PE (not available for size 0402)
PF (not available for size 0402)
100 min., 1 mult
100 min., 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500 min., 2500 mult
Full tape (quantity depending on size of chips)
100 min., 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500 min., 2500 mult
Full tape (quantity depending on size of chips)
TYPICAL HIGH FREQUENCY PERFORMANCE ELECTRICAL MODEL
Z
C
Z
0
C
g
L
c
L
R
L
c
C
g
Z
0
C
L
R
Z
L
c
C
g
Revision: 08-Feb-2019
Internal shunt capacitance
Internal inductance
Resistance
Internal impedance (R, L, C)
External connection inductance
External capacitance to ground
Document Number: 53014
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH
www.vishay.com
The complex impedance of the chip resistor is given by the following equations:
R
+
j
L
–
R
C
–
L C
Z
=
-------------------------------------------------------------------------------------
-
2
2
2
4
1
+
C
R
C
–
2L
+
L C
1
Z
=
-----------------------------------------------------------------------------------------
x
-
-------
-
2
2
2
4
R
1
+
C
R
C
–
2L
+
L C
–
1
L
2
2
2
2
Vishay Sfernice
L
–
R
C
–
L C
1
+
-----------------------------------------------------------
-
R
2
2
2
2
2
2
Notes
•
=2x
x
f
•
f:
Frequency
–
R
C
–
L C
=
tan
-----------------------------------------------------------
-
R
R, L and C are relevant to the chip resistor itself.
L
c
and C
g
also depend on the way the chip resistor is mounted.
It is important to notice that after assembly the external reactance of L
c
and C
g
will be combined to internal reactance of L and
C. This combination can upgrade or downgrade the HF behavior of the component.
This is why we are displaying three sets of data:
Z
•
-------
versus frequency curves which aim to show at a glance the intrinsic HF performance of a given chip resistor
-
R
Z
total
•
------------------
versus frequency curves which aim to show the behavior of the chip resistor when mounted
-
R
These lines are terminated with adapted source and load impedance respectively Z
s
and Z
l
with Z
0
= Z
L
= Z
s
(for others
configurations please consult us).
Equivalent circuit for S-parameters:
Z total
C
Z
S
Z
0
C
g
L
c
L
R
L
c
C
g
Z
0
Z
L
G
S-parameters are computed taking into account all the resistive, inductive and capacitive elements (Z total) and Z
0
= Z
L
= Z
s
=
R.
For simulation purposes, those S-parameter data are available for download here:
www.vishay.com/doc?53061
Revision: 08-Feb-2019
Document Number: 53014
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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