ISO
2
-CMOS ST-BUS FAMILY MT9171/72
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Data Sheet
March 2013
Features
•
•
•
•
•
•
•
•
•
Full-duplex transmission over a single twisted pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3 km (9171) and 4 km (9172)
Integrated services digital network (ISDN)
compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Microsemi
®
ST-BUS compatible
Low power (typically 50 mW), single 5 V supply
Ordering Information
MT9171/72AP1
MT9171/72AN1
MT9171/72APR1
MT9171/72ANR1
*Pb
28 Pin PLCC*
24 Pin SSOP*
28 Pin PLCC*
24 Pin SSOP*
Free Matte Tin
Tubes
Tubes
Tape & Reel
Tape & Reel
-40C to +85C
Description
The MT9171 (DSIC) and MT9172 (DNIC) are pins for
pin compatible replacements for the MT8971 and
MT8972, respectively. They are multi-functional
devices capable of providing high speed, full-duplex
digital transmission up to 160 kbit/s over a twisted wire
pair. They use adaptive echo-cancelling techniques
and transfer data in (2B+D) format compatible to the
ISDN basic rate. Several modes of operation allow an
easy interface to digital telecommunication networks
including use as a high speed limited distance modem
with data rates up to 160 kbit/s. Both devices function
identically but with the DSIC having a shorter
maximum loop reach specification. The generic "DNIC"
is used to reference both devices unless otherwise
noted. The MT9171/72 is fabricated in Microsemi
ISO
2
-CMOS process.
Applications
•
•
•
•
Digital subscriber lines
High speed data transmission over twisted wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
Address
Echo Canceller
Error
Signal
Echo Estimate
—
DPLL
V
Bias
MUX
L
OUT
DIS
Precan
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
1
Copyright 2013, Microsemi Corporation. All Rights Reserved.
MT9171/72
Change Summary
Data Sheet
Below are the changes made in March 2013 issue. Page, section, figure, and table numbers refer to this current
issue.
Page
Multiple
1
Item
Zarlink logo and name reference
“Ordering Information“
Change
Updated to Microsemi
®
logo and name.
Removed the following packages:
• MT9171/72AE 22 Pin PDIP
• MT9171/72AN 24 Pin SSOP
• MT9171/72AP 28 Pin PLCC
• MT9171/72APR 28 Pin PLCC
• MT9171/72ANR 24 Pin SSOP
• MT9171/72AE1 22 Pin PDIP*
Removed 22 pin PDIP diagram.
Removed the first column on 22 pin PDIP pin assignment.
Changed unit from 'ms' to 'us' for items 1, 2, 4, 5, 6, and 7.
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tubes
3
3
22
Figure 2
“Pin Description“
“AC Electrical Characteristics† -
Clock Timing - MOD Mode (Figure
18)“
“Performance Characteristics of the
MT9171 DSIC“
23
Corrected item 1 test conditions to SNR
≧
16.5dB.
2
Microsemi Corporation
MT9171/72
Data Sheet
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
24
1
2
3
4,5,6
28
2
3
4
5,7,8
Name
L
OUT
V
Bias
V
Ref
Description
Line Out.
Transmit Signal output (Analog). Referenced to V
Bias
.
Internal Bias Voltage
output. Connect through 0.33
F
decoupling capacitor to V
DD
.
Internal Reference Voltage
output. Connect via 0.33
F
decoupling capacitor to
V
DD
.
MS2-MS0
Mode Select
inputs (Digital). The logic levels present on these pins select the
various operating modes for a particular application. See Table 1 on page 9 for the
operating modes.
RegC
F0/CLD
Regulator Control
output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
Frame Pulse/C-Channel Load
(Digital). In DN mode a 244 ns wide negative pulse
input for the MASTER indicating the start of the active channel times of the device.
Output for the SLAVE indicating the start of the active channel times of the device.
Output in MOD mode providing a pulse indicating the start of the C-channel.
Control/Data ST-BUS In/Control/Data In
(Digital). A 2.048 Mbit/s serial control &
signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit
rate selected.
Control/Data ST-BUS Out/Control/Data Out
(Digital). A 2.048 Mbit/s serial control
& signalling output in DN mode. In MOD mode this is a continuous bit stream at the
bit rate selected.
Negative Power Supply
(0 V).
7
9
9
10
10
12
CDSTi/
CDi
CDSTo/
CDo
V
SS
11
13
12
13
14
14
15
16
DSTo/Do
Data ST-BUS Out/Data Out
(Digital). A 2.048 Mbit/s serial PCM/data output in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
DSTi/Di
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN mode.
In MOD mode this is a continuous bit stream at the bit rate selected.
3
Microsemi Corporation
CDSTi/CDi
CDSTo/CDo
VSS
DSTo/Do
DSTi/Di
F0o/RCK
NC
LOUT
VBias
VRef
MS2
MS1
MS0
RegC
NC
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
NC
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
4
3
2
1
28
27
26
VRef
VBias
LOUT
NC
VDD
LIN
TEST
12
13
14
15
16
17
18
MS2
NC
MS1
MS0
RegC
F0/CLD
NC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
LOUT DIS
Precan
OSC1
OSC2
NC
C4/TCK
28 PIN PLCC
MT9171/72
Pin Description (continued)
Pin #
24
15
28
17
Name
Description
Data Sheet
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode
this pin provides the transmit bit rate clock to the system.
Oscillator Output.
CMOS Output.
Oscillator Input.
CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1
’,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When logic
’0’, the L
OUT
to the precanceller path is enabled and functions normally. An internal
pulldown (50 k) is provided on this pin.
No Connection.
Leave open circuit
16
19
17
19
20
21
22
23
OSC2
OSC1
Precan
8,18
1,6,
11,
18,
20,
25
24
NC
21
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When
logic “0”, L
OUT
functions normally. An internal pull-down (50 k) is provided on this
pin.
TEST
L
IN
V
DD
Test Pin.
Connect to V
SS
.
Receive Signal
input (Analog).
Positive Power Supply
(+5 V) input.
22
23
24
26
27
28
F0
C4
DSTi
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
DSTo
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
F0o
Channel Time 0
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)
4
Microsemi Corporation
MT9171/72
Data Sheet
F0
C4
DSTi
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B2
7
B2
6
B2
5
B2
4
B2
3
B2
2
B2
1
B2
0
B1
7
DSTo
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B2
7
B2
6
B2
5
B2
4
B2
3
B2
2
B2
1
B2
0
B1
7
F0o
Channel Time 0
Channel Time 16
Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)
Functional Description
The MT9171/72 is a device which may be used in practically any application that requires high speed data
transmission over two wires, including smart telephone sets, workstations, data terminals and computers. The
device supports the 2B+D channel format (two 64 kbit/s B-channels and one 16 kbit/s D-channel) over two wires as
recommended by the CCITT. The line data is converted to and from the ST-BUS format on the system side of the
network to allow for easy interfacing with other components such as the S-interface device in an NT1 arrangement,
or to digital PABX components.
Smart telephone sets with data and voice capability can be easily implemented using the MT9171/72 as a line
interface. The device’s high bandwidth and long loop length capability allow its use in a wide variety of sets. This
can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in
both the home and central office or remote concentration equipment. Within the subscriber equipment the
MT9171/72 would terminate the line and encode/ decode the data and voice for transmission while additional
electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard
data rates for such things as computer communications and telemetry for remote meter reading. Digital
workstations with a high degree of networking capability can be designed using the DNIC for the line interface,
offering up to 160 kbit/s data transmission over existing telephone lines. The MT9171/72 could also be valuable
within existing computer networks for connecting a large number of terminals to a computer or for intercomputer
links. With the DNIC, this can be accomplished at up to 160 kbit/s at a very low cost per line for terminal to
computer links and in many cases this bandwidth would be sufficient for computer to computer links.
Figure 1 shows the block diagram of the MT9171/72. The DNIC provides a bidirectional interface between the DV
(data/voice) port and a full-duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. The DNIC
has three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo), and a
line port (L
IN
, L
OUT
). The data on the line is made up of information from the DV and CD ports. The DNIC must
combine information received from both the DV and CD ports and put it onto the line. At the same time, the data
received from the line must be split into the various channels and directed to the proper ports. The usable data
rates are 72 and 144 kbit/s as required for the basic rate interface in ISDN. Full-duplex transmission is made
possible through on board adaptive echo cancellation.
5
Microsemi Corporation
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
