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Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Complete Data Sheet
Product Specification
DS083 (v5.0) June 21, 2011
0
Module 1:
Introduction and Overview
10 pages
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Summary of Features
General Description
Architecture
IP Core and Reference Support
Device/Package Combinations and Maximum I/O
Ordering Information
Module 3:
DC and Switching Characteristics
59 pages
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Electrical Characteristics
Performance Characteristics
Switching Characteristics
Pin-to-Pin Output Parameter Guidelines
Pin-to-Pin Input Parameter Guidelines
DCM Timing Parameters
Source-Synchronous Switching Characteristics
Module 2:
Functional Description
60 pages
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Functional Description: RocketIO™ X Multi-Gigabit
Transceiver
Functional Description: RocketIO Multi-Gigabit
Transceiver
Functional Description: Processor Block
Functional Description: PowerPC™ 405 Core
Functional Description: FPGA
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Input/Output Blocks (IOBs)
Digitally Controlled Impedance (DCI)
On-Chip Differential Termination
Configurable Logic Blocks (CLBs)
3-State Buffers
CLB/Slice Configurations
18-Kb Block SelectRAM™ Resources
18-Bit x 18-Bit Multipliers
Global Clock Multiplexer Buffers
Digital Clock Manager (DCM)
Module 4:
Pinout Information
302 pages
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Pin Definitions
Pinout Tables
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FG256/FGG256 Wire-Bond Fine-Pitch BGA Package
FG456/FGG456 Wire-Bond Fine-Pitch BGA Package
FG676/FGG676 Wire-Bond Fine-Pitch BGA Package
FF672 Flip-Chip Fine-Pitch BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
FF1148 Flip-Chip Fine-Pitch BGA Package
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
FF1696 Flip-Chip Fine-Pitch BGA Package
FF1704 Flip-Chip Fine-Pitch BGA Package
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Routing
Configuration
IMPORTANT NOTE:
Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v5.0) June 21, 2011
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Introduction and Overview
Product Specification
DS083 (v5.0) June 21, 2011
Summary of Virtex-II Pro™ / Virtex-II Pro X Features
•
High-Performance Platform FPGA Solution, Including
- Up to twenty RocketIO™ or RocketIO X embedded
Multi-Gigabit Transceivers (MGTs)
- Up to two IBM PowerPC™ RISC processor blocks
Based on Virtex-II™ Platform FPGA Technology
- Flexible logic resources
- SRAM-based in-system configuration
- Active Interconnect technology
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SelectRAM™+ memory hierarchy
Dedicated 18-bit x 18-bit multiplier blocks
High-performance clock management circuitry
SelectI/O™-Ultra technology
XCITE Digitally Controlled Impedance (DCI) I/O
•
Virtex-II Pro / Virtex-II Pro X family members and resources
are shown in
Table 1.
Table 1:
Virtex-II Pro / Virtex-II Pro X FPGA Family Members
CLB (1 = 4 slices =
max 128 bits)
Logic
Cells
(2)
3,168
6,768
11,088
20,880
22,032
30,816
43,632
53,136
74,448
74,448
99,216
Slices
1,408
3,008
4,928
9,280
9,792
13,696
19,392
23,616
33,088
33,088
44,096
Max Distr
RAM (Kb)
44
94
154
290
306
428
606
738
1,034
1,034
1,378
Block SelectRAM+
18 Kb Max Block
Blocks RAM (Kb)
12
28
44
88
88
136
192
232
328
308
444
216
504
792
1,584
1,584
2,448
3,456
4,176
5,904
5,544
7,992
DCMs
4
4
4
8
8
8
8
8
8
8
12
Device
(1)
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VPX20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
Notes:
1.
2.
3.
4.
RocketIO
Transceiver
Blocks
4
4
8
8
8
(4)
8
0
(3)
, 8, or 12
0
(3)
or 16
16 or 20
20
(4)
0
(3)
or 20
PowerPC
Processor
Blocks
0
1
1
2
1
2
2
2
2
2
2
18 X 18 Bit
Multiplier
Blocks
12
28
44
88
88
136
192
232
328
308
444
Maximum
User
I/O Pads
204
348
396
564
552
644
804
852
996
992
1,164
-7 speed grade devices are not available in Industrial grade.
Logic Cell
(1) 4-input LUT + (1)FF + Carry Logic
These devices can be ordered in a configuration without RocketIO transceivers. See
Table 3
for package configurations.
Virtex-II Pro X devices equipped with RocketIO X transceiver cores.
RocketIO X Transceiver Features (XC2VPX20 and XC2VPX70 Only)
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Variable-Speed Full-Duplex Transceiver (XC2VPX20)
Allowing 2.488 Gb/s to 6.25 Gb/s Baud Transfer Rates.
- Includes specific baud rates used by various
standards, as listed in
Table 4, Module 2.
Fixed-Speed Full-Duplex Tranceiver (XC2VPX70)
Operating at 4.25 Gb/s Baud Transfer Rate.
Eight or Twenty Transceiver Modules on an FPGA,
Depending upon Device
Monolithic Clock Synthesis and Clock Recovery
- Eliminates the need for external components
•
•
Automatic Lock-to-Reference Function
Programmable Serial Output Differential Swing
- 200 mV to 1600 mV, peak-peak
- Allows compatibility with other serial system
voltage levels
Programmable Pre-emphasis Levels 0 to 500%
Telecom/Datacom Support Modes
- "x8" and "x10" clocking/data paths
- 64B/66B clocking support
•
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•
•
•
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Internal Loopback Modes for Testing Operability
Programmable Comma Detection
- Allows for any protocol
- Allows for detection of any 10-bit character
8B/10B and 64B/66B Encoding Blocks
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Programmable Receiver Equalization
Internal AC Coupling
On-Chip 50Termination
- Eliminates the need for external termination
resistors
Pre- and Post-Driver Serial and Parallel TX-to-RX
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RocketIO Transceiver Features (All Except XC2VPX20 and XC2VPX70)
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Full-Duplex Serial Transceiver (SERDES) Capable of
Baud Rates from 600 Mb/s to 3.125 Gb/s
100 Gb/s Duplex Data Rate (20 Channels)
Monolithic Clock Synthesis and Clock Recovery (CDR)
Fibre Channel, 10G Fibre Channel, Gigabit Ethernet,
10 Gb Attachment Unit Interface (XAUI), and
Infiniband-Compliant Transceivers
8-, 16-, or 32-bit Selectable Internal FPGA Interface
8B /10B Encoder and Decoder (optional)
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50 /75 on-chip Selectable Transmit and Receive
Terminations
Programmable Comma Detection
Channel Bonding Support (from 2 to 20 Channels)
Rate Matching via Insertion/Deletion Characters
Four Levels of Selectable Pre-Emphasis
Five Levels of Output Differential Voltage
Per-Channel Internal Loopback Modes
2.5V Transceiver Supply Voltage
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PowerPC RISC Processor Block Features (All Except XC2VP2)
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Embedded 300+ MHz Harvard Architecture Block
Low Power Consumption: 0.9 mW/MHz
Five-Stage Data Path Pipeline
Hardware Multiply/Divide Unit
Thirty-Two 32-bit General Purpose Registers
16 KB Two-Way Set-Associative Instruction Cache
16 KB Two-Way Set-Associative Data Cache
•
Memory Management Unit (MMU)
- 64-entry unified Translation Look-aside Buffers (TLB)
- Variable page sizes (1 KB to 16 MB)
Dedicated On-Chip Memory (OCM) Interface
Supports IBM CoreConnect™ Bus Architecture
Debug and Trace Support
Timer Facilities
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Virtex-II Pro Platform FPGA Technology (All Devices)
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SelectRAM+ Memory Hierarchy
- Up to 8 Mb of True Dual-Port RAM in 18 Kb block
SelectRAM+ resources
- Up to 1,378 Kb of distributed SelectRAM+
resources
- High-performance interfaces to external memory
Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
Flexible Logic Resources
- Up to 88,192 internal registers/latches with Clock
Enable
- Up to 88,192 look-up tables (LUTs) or cascadable
variable (1 to 16 bits) shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and Sum-of-Products
support
- Internal 3-state busing
High-Performance Clock Management Circuitry
- Up to twelve Digital Clock Manager (DCM) modules
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Precise clock de-skew
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Flexible frequency synthesis
High-resolution phase shifting
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- 16 global clock multiplexer buffers in all parts
Active Interconnect Technology
- Fourth-generation segmented routing structure
- Fast, predictable routing delay, independent of
fanout
- Deep sub-micron noise immunity benefits
SelectIO™-Ultra Technology
- Up to 1,164 user I/Os
- Twenty-two single-ended standards and
ten differential standards
- Programmable LVCMOS sink/source current (2 mA
to 24 mA) per I/O
- XCITE Digitally Controlled Impedance (DCI) I/O
- PCI/ PCI-X support
(1)
- Differential signaling
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840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
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On-chip differential termination
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Bus LVDS I/O
1. Refer to
XAPP653
for more information.
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
- Readback capability
Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
- Integrated VHDL and Verilog design flows
- ChipScope™ Integrated Logic Analyzer
0.13 µm Nine-Layer Copper Process with 90 nm
High-Speed Transistors
1.5V (V
CCINT
) core power supply, dedicated 2.5V
V
CCAUX
auxiliary and V
CCO
I/O power supplies
IEEE 1149.1 Compatible Boundary-Scan Logic Support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Standard 1.00 mm Pitch.
Wire-Bond BGA Devices Available in Pb-Free
Packaging (www.xilinx.com/pbfree)
Each Device 100% Factory Tested
·
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HyperTransport (LDT) I/O with current driver
buffers
Built-in DDR input and output registers
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Proprietary high-performance SelectLink
technology for communications between Xilinx
devices
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High-bandwidth data path
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Double Data Rate (DDR) link
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Web-based HDL generation methodology
SRAM-Based In-System Configuration
- Fast SelectMAP™ configuration
- Triple Data Encryption Standard (DES) security
option (bitstream encryption)
- IEEE 1532 support
- Partial reconfiguration
- Unlimited reprogrammability
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•
General Description
The Virtex-II Pro and Virtex-II Pro X families contain plat-
form FPGAs for designs that are based on IP cores and
customized modules. The family incorporates multi-gigabit
transceivers and PowerPC CPU blocks in Virtex-II Pro
Series FPGA architecture. It empowers complete solutions
for telecommunication, wireless, networking, video, and
DSP applications.
The leading-edge 0.13 µm CMOS nine-layer copper pro-
cess and Virtex-II Pro architecture are optimized for high
performance designs in a wide range of densities. Combin-
ing a wide variety of flexible features and IP cores, the
Virtex-II Pro family enhances programmable logic design
capabilities and is a powerful alternative to mask-pro-
grammed gate arrays.
•
•
•
Block SelectRAM+ memory modules provide large
18 Kb storage elements of True Dual-Port RAM.
Embedded multiplier blocks are 18-bit x 18-bit
dedicated multipliers.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, and coarse- and fine-grained clock phase
shifting.
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all these ele-
ments. The general routing matrix (GRM) is an array of rout-
ing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and supports high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Architecture
Array Overview
Virtex-II Pro and Virtex-II Pro X devices are user-program-
mable gate arrays with various configurable elements and
embedded blocks optimized for high-density and high-per-
formance system designs. Virtex-II Pro devices implement
the following functionality:
•
Embedded high-speed serial transceivers enable data
bit rate up to 3.125 Gb/s per channel (RocketIO) or
6.25 Gb/s (RocketIO X).
Embedded IBM PowerPC 405 RISC processor blocks
provide performance up to 400 MHz.
SelectIO-Ultra blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported
by the programmable IOBs.
Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
Features
This section briefly describes Virtex-II Pro / Virtex-II Pro X
features. For more details, refer to
Virtex-II Pro and
Virtex-II Pro X Platform FPGAs: Functional Description.
•
•
RocketIO / RocketIO X MGT Cores
The RocketIO and RocketIO X Multi-Gigabit Transceivers
are flexible parallel-to-serial and serial-to-parallel embed-
ded transceiver cores used for high-bandwidth interconnec-
tion between buses, backplanes, or other subsystems.
Multiple user instantiations in an FPGA are possible,
providing up to 100 Gb/s (RocketIO) or 170 Gb/s
(RocketIO X) of full-duplex raw data transfer. Each channel
can be operated at a maximum data transfer rate of
3.125 Gb/s (RocketIO) or 6.25 Gb/s (RocketIO X).
•
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Separate instruction and data cache units, both
two-way set-associative and non-blocking
- Eight words (32 bytes) per cache line
- 16 KB array Instruction Cache Unit (ICU), 16 KB
array Data Cache Unit (DCU)
- Operand forwarding during instruction cache line fill
- Copy-back or write-through DCU strategy
- Doubleword instruction fetch from cache improves
branch latency
Virtual mode memory management unit (MMU)
- Translation of the 4 GB logical address space into
physical addresses
- Software control of page replacement strategy
- Supports multiple simultaneous page sizes ranging
from 1 KB to 16 MB
OCM controllers provide dedicated interfaces between
Block SelectRAM+ memory and processor block
instruction and data paths for high-speed access
PowerPC timer facilities
- 64-bit time base
- Programmable interval timer (PIT)
- Fixed interval timer (FIT)
- Watchdog timer (WDT)
Debug Support
- Internal debug mode
- External debug mode
- Debug Wait mode
- Real Time Trace debug mode
- Enhanced debug support with logical operators
- Instruction trace and trace-back support
- Forward or backward trace
Two hardware interrupt levels support
Advanced power management support
-
Each RocketIO or RocketIO X core implements the following
technology:
•
•
•
Serializer and deserializer (SERDES)
Monolithic clock synthesis and clock recovery (CDR)
10 Gigabit Attachment Unit Interface (XAUI) Fibre
Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express,
Aurora, SXI-5 (SFI-5,/SPI-5), and OC-48
compatibility
(1)
8/16/32-bit (RocketIO) or 8/16/32/64-bit (RocketIO X)
selectable FPGA interface
8B/10B (RocketIO) or 8B/10B and 64B/66B
(RocketIO X) encoder and decoder with bypassing
option on each channel
Channel bonding support (two to twenty channels)
- Elastic buffers for inter-chip deskewing and
channel-to-channel alignment
Receiver clock recovery tolerance of up to
75 non-transitioning bits
50 (RocketIO X) or 50 /75 selectable (RocketIO)
on-chip transmit and receive terminations
Programmable comma detection and word alignment
Rate matching via insertion/deletion characters
Automatic lock-to-reference function
Programmable pre-emphasis support
Per-channel serial and parallel transmitter-to-receiver
internal loopback modes
Optional transmit and receive data inversion
Cyclic Redundancy Check support (RocketIO only)
•
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•
PowerPC 405 Processor Block
The PPC405 RISC CPU can execute instructions at a sus-
tained rate of one instruction per cycle. On-chip instruction
and data cache reduce design complexity and improve sys-
tem throughput.
The PPC405 features include:
•
PowerPC RISC CPU
- Implements the PowerPC User Instruction Set
Architecture (UISA) and extensions for embedded
applications
- Thirty-two 32-bit general purpose registers (GPRs)
- Static branch prediction
- Five-stage pipeline with single-cycle execution of
most instructions, including loads/stores
- Unaligned and aligned load/store support to cache,
main memory, and on-chip memory
- Hardware multiply/divide for faster integer
arithmetic (4-cycle multiply, 35-cycle divide)
- Enhanced string and multiple-word handling
- Big/little endian operation support
Storage Control
•
•
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
•
•
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
Output block with an optional SDR or DDR register and
an optional 3-state buffer to be driven directly or
through an SDR or DDR register
Bidirectional block (any combination of input and output
configurations)
•
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
•
•
•
•
LVTTL, LVCMOS (3.3V,
(2)
2.5V, 1.8V, and 1.5V)
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
(3)
PCI compliant (66 MHz and 33 MHz) at 3.3V
(3)
GTL and GTLP
•
1. Refer to
Table 4, Module 2
for detailed information about RocketIO and RocketIO X transceiver compatible protocols.
2. Refer to
XAPP659
for more information.
3. Refer to
XAPP653
for more information.
DS083 (v5.0) June 21, 2011
Product Specification
www.xilinx.com
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