DIFFERENTIAL-TO-HSTL ZERO DELAY
CLOCK GENERATOR
ICS8725-21
Features
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One differential HSTL output pair
One differential feedback output pair
Differential CLK/nCLK input pair
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 630MHz
Input frequency range: 31.25MHz to 630MHz
VCO range: 250MHz to630MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 35ps (maximum)
Output skew: 50ps (maximum)
Static phase offset: 30ps ± 125ps
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Industrial temperature information available upon request
General Description
The ICS8725-21 is a highly versatile 1:1 Differential-
to-HSTL Clock Generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The CLK, nCLK pair can accept
most standard differential input levels. The
ICS8725-21 has a fully integrated PLL and can be configured as
zero delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 630MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
ICS
Block Diagram
PLL_SEL
Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
CLK
Pulldown
nCLK
Pullup
0
Q
nQ
Pin Assignment
CLK
nCLK
MR
V
DD
nFB_IN
FB_IN
SEL2
GND
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
V
DDO
Q
nQ
1
QFB
nQFB
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
Pulldown
nFB_IN
Pullup
ICS8725-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
IDT™ / ICS™
HSTL ZERO DELAY CLOCK GENERATOR
1
ICS8725AM-21 REV. A FEBRUARY 27, 2008
ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1
2
Name
CLK
nCLK
Input
Input
Type
Pulldown
Pullup
Description
Non-inverting differential clock input.
Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Pulldown
Pulldown
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 9.
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 10.
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Power supply ground.
Differential feedback output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Output supply pin.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
No connect.
3
MR
Input
Pulldown
4, 17
5
6
7, 14,
18, 19
8
9, 10
11, 12
13
15
16
20
V
DD
nFB_IN
FB_IN
SEL2, SEL3,
SEL0 SEL1
GND
nQFB, QFB
nQ/Q
V
DDO
V
DDA
PLL_SEL
nc
Power
Input
Input
Input
Power
Output
Output
Power
Power
Input
Unused
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
IDT™ / ICS™
HSTL ZERO DELAY CLOCK GENERATOR
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ICS8725AM-21 REV. A FEBRUARY 27, 2008
ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)*
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
125 - 315
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
62.5 - 157.5
31.25 - 78.75
31.25 - 78.75
Q/nQ
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*NOTE: VCO frequency range for all configurations above is 250MHz to 630MHz.
IDT™ / ICS™
HSTL ZERO DELAY CLOCK GENERATOR
3
ICS8725AM-21 REV. A FEBRUARY 27, 2008
ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q/nQ, QFB/nQFB
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
SEL3
0z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IDT™ / ICS™
HSTL ZERO DELAY CLOCK GENERATOR
4
ICS8725AM-21 REV. A FEBRUARY 27, 2008
ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
46.2°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDA
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
0
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
3.3
1.8
Maximum
3.465
3.465
2.0
137
17
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDA
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
SEL[0:3], MR
Input High Current
PLL_SEL
SEL[0:3], MR
I
IL
Input Low Current
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
IDT™ / ICS™
HSTL ZERO DELAY CLOCK GENERATOR
5
ICS8725AM-21 REV. A FEBRUARY 27, 2008
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