Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
F
EATURES
• Twenty LVCMOS outputs, 7Ω typical output impedance
• One differential clock input pair
• CLK, nCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 250MHz
• Translates any differential input signal (LVPECL, LVHSTL,
LVDS) to LVCMOS levels without external bias networks
• Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
• Bank enable logic allows unused banks to be disabled in
reduced fanout applications
• Output skew: 200ps (maximum)
• Bank skew: 150ps (maximum)
• Part-to-part skew: 650ps (maximum)
• Multiple frequency skew: 250ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• Available in both standard and lead-free RoHS compliant
packages
ICS8702
G
ENERAL
D
ESCRIPTION
The ICS8702 is a low skew,
÷1, ÷2
Differential-to-
LVCMOS Clock Generator and a member of the
HiPerClockS™
HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS8702 is designed to
translate any differential signal levels to
LVCMOS/LVTTL levels. True or inverting, single-ended to
LVCMOS translation can be achieved with a resistor bias
on the nCLK or CLK inputs, respectively. The effective fan-
out can be increased from 20 to 40 by utilizing the ability of
the outputs to drive two series terminated lines.
IC
S
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1, ÷2
or a combination of ÷1 and ÷2 modes. The bank enable in-
puts, BANK_EN0:1, supports enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
enabling and disabling of all outputs simultaneously.
The ICS8702 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output, multiple frequency and part-to-part skew char-
acteristics make the ICS8702 ideal for those clock dis-
tribution applications demanding well defined performance
and repeatability.
B
LOCK
D
IAGRAM
CLK
nCLK
DIV_SELA
1
QB0:QB4
0
DIV_SELB
1
0
DIV_SELC
1
0
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
QD0:QD4
QC0:QC4
÷
1
÷
2
1
0
QA0:QA4
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
QC3
V
DDO
QC4
QD0
V
DDO
QD1
GND
QD2
GND
QD3
V
DDO
QD4
ICS8702
QB1
V
DDO
QB0
QA4
V
DDO
QA3
GND
QA2
GND
QA1
V
DDO
QA0
8702BY
www.icst.com/products/hiperclocks.com
1
DIV_SELA
DIV_SELB
CLK
nCLK
V
DD
BANK_EN0
GND
BANK_EN1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
REV. D OCTOBER 28, 2008
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
Type
Power
Description
Output supply pins.
ICS8702
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
2, 5, 11, 26,
32, 35, 41, 44
7, 9, 18,
28, 30, 37,
39, 46, 48
16, 20
25, 27, 29,
31, 33
34, 36, 38,
40, 42
43, 45, 47,
1, 3
4, 6, 8,
10, 12
22
21
Name
V
DDO
GND
V
DD
QA0, QA1, QA2,
QA3, QA4
QB0, QB1, QB2,
QB3, QB4
QC0, QC1, QC2,
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
CLK
nCLK
Power
Power
Output
Output
Output
Output
Input
Input
Output power supply.
Positive supply pins.
Bank A outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL interface levels.
Bank B outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL interface levels.
Bank C outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL interface levels.
Bank D outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Controls frequency division for Bank D outputs.
13
DIV_SELD
Input
Pullup
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank C outputs.
14
DIV_SELC
Input
Pullup
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank B outputs
23
DIV_SELB
Input
Pullup
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank A outputs.
Pullup
24
DIV_SELA
Input
LVCMOS/LVTTL interface levels.
Enables and disables outputs by banks.
BANK_EN1,
Pullup
17, 19
Input
LVCMOS/LVTTL interface levels.
BANK_EN0
Master Reset and output enable. When HIGH, output drivers are
enabled. When LOW, output drivers are in HiZ and dividers are
15
nMR/OE
Input
Pullup
reset. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
V
DD
= V
DDO
= 3.465V
7
15
Maximum
Units
pF
kΩ
kΩ
pF
Ω
8702BY
www.icst.com/products/hiperclocks.com
2
REV. D OCTOBER 28, 2008
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the
DC Characteristics
or
AC
Characteristics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
ICS8702
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
95
Units
V
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2. 5
Maximum
3.465
2.625
95
Units
V
V
mA
T
ABLE
4C. LVCMOS /LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
V
IH
Parameter
Input
High Voltage
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
Test Conditions
Minimum
2
Typical
Maximum
V
DD
+ 0.3
Units
V
V
IL
Input
Low Voltage
-0.3
0.8
V
I
IH
Input
High Current
V
DD
= V
IN
= 3.465V
5
µA
I
IL
Input
Low Current
V
DD
= 3.465V, V
IN
= 0V
V
DD
= V
DDO
= 3.135V
I
OH
= -36mA
V
DD
= V
DDO
= 3.135V
I
OL
= 36mA
-150
µA
V
OH
V
OL
Output High Voltage
Output Low Voltage
2.6
0.5
V
V
8702BY
www.icst.com/products/hiperclocks.com
4
REV. D OCTOBER 28, 2008
微控制器 MCU
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