Freescale Semiconductor
Advance Information
Document Number: 34844
Rev. 3.0, 11/2008
10 Channel LED Backlight Driver
with Integrated Power Supply
The 34844 is a high efficiency, LED driver for use in backlighting
LCD displays from 10" to 20"+. Operating from supplies of 7V to 28V,
the 34844 is capable of driving up to 160 LEDs in 10 parallel strings.
Current in the 10 strings is matched to within
±2%,
and can be
programmed via the I
2
C/SM-Bus interface.
The 34844 also includes a Pulse Width Monitor (PWM) generator
for LED dimming. The LEDs can be dimmed to one of 256 levels,
programmed through the I
2
C/SM-Bus interface. Up to 65,000:1 (256:1
PWM, 256:1 Current DAC) dimming ratio.
The integrated boost converter generates the minimum output
voltage required to keep all LEDs illuminated with the selected current,
providing the highest efficiency possible. The integrated boost self-
clocks at a default frequency of 600kHz, but may be programmed via
I
2
C to 150/300/600/1200 kHz. The PWM frequency can be set from
100Hz to 25kHz, or can be synchronized to an external input. If not
synchronized to another source, the internal PWM rate outputs on the
CK pin. This enables multiple devices to be synchronized together.
The 34844 also supports optical/temperature closed loop operation
and also features LED over-temperature protection, LED short
protection, and LED open circuit protection. The IC also includes over-
voltage protection, over-current protection, and under-voltage lockout.
Features
• Input voltage of 7.0 to 28V
• Boost output voltage up to 60V, with Dynamic
Headroom Control (DHC)
• 3.0A integrated boost FET
• Up to 50mA LED current per channel
• 90% efficiency (DC:DC)
• 10-channel current mirror with ±2% current matching
• I
2
C/SM-Bus interface
• PWM frequency programmable or synchronizable from
100Hz to 25,000Hz
• 32-Ld 5x5x1.0mm TQFN Package
• Pb-free packaging designated by suffix code EP
7.0 to 28V
34844
LED DRIVER
EP SUFFIX (PB-FREE)
98ASA10800D
32-PIN QFN-EP
ORDERING INFORMATION
Device
MC34844EP/R2
Temperature
Range (T
A
)
-40°C to 105°C
Package
32 QFN-EP
Applications
•
•
•
•
Monitors - up to 27 inch
Personal Computer Notebooks
GPS Screens
Small screen Televisions
34844
VIN
VDC1
VDC2
VDC3
COMP
SLOPE
SCK
SDA
PWM
A0/SEN
CK
M/~S
EN
VDC1
ISET
PIN
NIN
GND
VOUT
PGNDA
PGNDB
FAIL
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
VCC
SWA
SWB
Control Unit
VDC1
~
~
~
~
~
~
~
~
~
~
VDC1
Figure 1. Simplified Application Diagram (SM-Bus Mode)
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIN
VDC1
VDC2
VDC3
COMP
SLOPE
VOUT
CK
EN
M/~S
PWM
PWM GENERATOR
I0
I1
I2
SCK
SDA
10 CHANNEL
50mA CURRENT
MIRROR
I3
I4
I5
I6
I7
I8
ISET
CURRENT DAC
I9
CLOCK/PLL
V SENSE
FAIL
BOOST
CONTROLLER
LDO
OVP
PGNDA
PGNDB
SWA
SWB
A0/SEN
I
2
C INTERFACE
PIN
NIN
TEMP/OPTO
LOOP CONTROL
OCP/OTP/UVLO
GND
Figure 2. 34844 Simplified Internal Block Diagram
34844
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
COMP
VOUT
VDC2
VDC1
PWM
25
24 CK
23 VDC3
TRANSPARENT
TOP VIEW
QFN - EP
5MM X 5MM
32 LEAD
EP GND
22 SLOPE
21 NIN
20 PIN
19 ISET
18 FAIL
17 I9
9
I1
10
I2
11
I3
12
I4
13
I5
14
I6
15
I7
16
I8
M/~S
SCK
27
SDA
26
32
VIN 1
PGNDB 2
SWB 3
SWA 4
PGNDA 5
A0/SEN 6
EN 7
IO 8
31
30
29
28
EP = Exposed Pad
Figure 3. 34844 Pin Connections
Table 1. 34844 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 11.
Pin Number
1
2
3
4
5
6
7
8 - 17
18
Pin Name
VIN
PGNDB
SWB
SWA
PGNDA
A0/SEN
EN
I0-I9
FAIL
Pin Function
Power
Power
Input
Input
Power
Input
Input
Input
Open Drain
Formal Name
Input voltage
Power Ground
Switch node B
Switch node A
Power Ground
Device Select
Enable
LED Channel
Fault detection
Input supply
Power ground
Boost switch connection B
Boost switch connection A
Power ground
Address select, device select pin or OVP HW control
Enable pin (active high, internal pull-up)
LED string connections
Fault detected pin (open drain):
No Failure = Low impedance
Failure = High Impedance
LED current setting resistor
Positive input analog current control
Definition
19
20
21
22
23
24
25
ISET
PIN
NIN
SLOPE
VDC3
CK
PWM
Passive
Input
Input
Passive
Output
Input/Output
Input
Current set
Positive current scale
Negative current scale Negative input analog current control
Boost Slope
Internal Regulator 3
Clock signal
External PWM
Boost slope compensation Setting resistor
Decoupling capacitor for internal phase locked loop power
Clock synchronization pin (input for M/~S = low - internal pull-up, output
for M/~S = high)
External PWM input (internal pull-down)
34844
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34844 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 11.
Pin Number
26
27
28
29
30
31
32
EP
Pin Name
SDA
SCK
VDC1
COMP
M/~S
VDC2
VOUT
GND
Pin Function
Bidirectional
Bidirectional
Output
Passive
Input
Output
Input
-
Formal Name
I
2
C data
I
2
C clock
Internal Regulator 1
Compensation pin
Master/Slave selector
Internal Regulator 2
Voltage Output
Ground
I
2
C data Line
I
2
C clock line
Decoupling capacitor for internal logic rail
Boost converter Type compensation pin
Selects Master Mode (1) or Slave Mode (0)
Decoupling capacitor for internal regulator
Boost Output voltage sense pin
Ground Reference for all internal circuits other than Boost FET
Definition
34844
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
Maximum Pin Voltages
A0/SEN
I0, I1, I2, I3, I4, I5, I6, I7, I8, I9,EN
(4)
VIN
SWA, SWB, VOUT
FAIL, PIN, NIN, ISET, M/~S, CK
Maximum LED Current
ESD Voltage
(1)
Human Body Model (HBM)
Machine Model (MM)
THERMAL RATINGS
Ambient Temperature Range
Junction to Ambient Temperature
(2)
Junction to Case Temperature
(2)
Maximum junction temperature
Storage temperature range
Peak Package Reflow Temperature During Reflow
(3)
Power Dissipation
TA = 25°C
TA = 70°C
TA = 85°C
TA = 105°C
3.9
2.5
2.0
1.4
T
A
T
θ
JA
T
θ
JC
T
J
T
STO
T
PPRT
-40 to 105
32
3.5
150
-40 to 150
260
°C
°C/W
°C/W
°C
°C
°C
W
I
MAX
V
ESD
+2000
+200
V
MAX
7.0
45
30
65
6.0
55
mA
V
V
Symbol
Value
Unit
Notes
1. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100-
003), R
ZAP
= 0Ω
2.
3.
4.
Per JEDEC51 Standard for Multilayer PCB
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
45V is the Maximum allowable voltage on all LED channels in off-state.
34844
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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