NCP5359A
Gate Driver for Notebook
Power Systems
The NCP5359A is a high performance dual MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. Each of the drivers can
drive up to 3 nF load with a 25 ns propagation delay and 15 ns
transition time.
Adaptive nonoverlap and power saving operation circuit can
provide a low switching loss and high efficiency solution for notebook
and desktop systems.
A high floating top driver design can accommodate VBST voltage
as high as 35 V, with transient voltages as high as 35 V. Bidirectional
EN pin can provide a fault signal to controller when the gate driver
fault detect under OVP, UVLO occur. Also, an undervoltage lockout
function guarantees the outputs are low when supply voltage is low,
and a thermal shutdown function provides the IC with
overtemperature protection.
Features
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MARKING
DIAGRAMS
8
8
1
A
L
Y
W
G
SOIC−8
D SUFFIX
CASE 751
5359A
ALYW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
DFN8
MN SUFFIX
CASE 506AA
•
•
•
•
•
•
•
•
•
•
Faster Rise and Fall Times
Thermal Shutdown Protection
Adaptive Nonoverlap Circuit
Floating Top Driver Accommodates Boost Voltages of up to 30 V
Output Disable Control Turns Off Both MOSFETs
Complies with VRM 11.1 Specifications
Undervoltage Lockout
Power Saving Operation Under Light Load Conditions
Thermally Enhanced Package
These are Pb−Free Devices
1
1
AA = Device Code
M = Date Code
G
= Pb−Free Package
PIN CONNECTIONS
BST
PWM
EN
V
CC
1
BST
PWM
EN
V
CC
(Top View)
8
DRVH
SW
GND
DRVL
1
8
DRVH
SW
GND
DRVL
Typical Applications
•
Power Solutions for Desktop and Notebook Systems
ORDERING INFORMATION
Device
NCP5359ADR2G
NCP5359AMNR2G
NCP5359AMNTBG
Package
SOIC−8
(Pb−Free)
DFN8
(Pb−Free)
DFN8
(Pb−Free)
Shipping
†
2500 Tape & Reel
3000 Tape & Reel
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2009
September, 2009
−
Rev. 1
1
Publication Order Number:
NCP5359A/D
AA M
G
4
NCP5359A
BST
VCC
ChipEN
Level Shift
and
Driver
DRVH
EN
Fault
PWM
DRVH Comparator
PWM > 2.2 V = 1, Else = 0
Falling Edge Delay
1.0 V
UVLO
Thermal Shutdown
FPWM Comparator
0.8 V < PWM < 2.2 V = 1,
Else 0
EN
Pre
−Over
voltage
Pre−OV
2 V/1 V
Falling Edge Delay
R
Q
S
Q
Driver
Pre−OV
+
−
Fault
ChipEN
SW
1 mV
l
+
+
−
ChipEN
GND
V
CC
DRVL
Figure 1. Internal Block Diagram
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2
+
−
+
l
SW
l
+
GND
NCP5359A
4 V to 15 V
BST
PWM
EN
10 V to 13.2 V
PWM
EN
VCC
DRVH
SW
GND
DRVL
VOUT
Figure 2. Typical Application
PIN DESCRIPTION
SOIC−8
1
2
DFN8
1
2
Symbol
BST
PWM
Description
Upper MOSFET Floating Bootstrap Supply Pin
PWM Input Pin
When PWM voltage is higher than 2.2 V, DRVH will set to 1 and DRVL set to 0
When PWM voltage is lower than 0.8 V, DRVL will set to 1 and DRVH set to 0
When 0.8 V < PWM < 2.2 V and SW < 0, DRVL will set to 1
When 0.8 V < PWM < 2.2 V and SW > 0, DRVL will set to 0
Enable Pin
When OVP, TSD or UVLO has happened, the gate driver will pull the pin to low
Connect to Input Power Supply 10 V to 13.2 V
Low Side Gate Drive Output
Ground Pin
Switch Node Pin
High Side Gate Drive Output
3
4
5
6
7
8
3
4
5
6
7
8
EN
VCC
DRVL
GND
SW
DRVH
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3
NCP5359A
MAXIMUM RATINGS
Rating
Thermal Characteristics, Plastic Package
Thermal Resistance Junction−to−Air
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
SOIC−8
DFN8
SOIC−8
(20.2 sq mm, 2 oz Cu) DFN8
Symbol
R
qJA
Value
178
330
0 to +150
0 to +85
−
55 to +150
1
1
Unit
°C/W
T
J
T
A
T
stg
MSL
°C
°C
°C
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
MAXIMUM RATINGS
Pin Symbol
Vcc
BST
Pin Name
Main Supply Voltage Input
Bootstrap Supply voltage
V
MAX
15 V
35 V wrt / GND
40 V
≤
50 ns wrt / GND
15 V wrt / SW
35 V wrt / GND
40 V
≤
50 ns wrt / GND
BST + 0.3 V
35 V
≤
50 ns wrt / GND
15 V wrt / SW
Vcc + 0.3 V
6V
6V
0V
V
MIN
−0.3
V
−0.3
V wrt / SW
SW
DRVH
Switching Node
(Bootstrap Supply Return)
High Side Driver Output
−1
VDC
−10
V (200 ns)
−0.3
V wrt / SW
−2
V (200 ns) wrt / SW
−0.3
V
−5
V (200 ns)
−0.3
V
−0.3
V
0V
DRVL
PWM
EN
GND
Low Side Driver Output
DRVH and DRVL Control Input
Enable Pin
Ground
1. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78.
2. Moisture Sensitivity Level (MSL): 1&3 per IPC/JEDEC standard: J−STD−020A.
3. The maximum package power dissipation limit must not be exceeded.
PD
+
NOTE:
TJ(max)
*
TA
RqJA
This device is ESD sensitive. Use standard ESD precautions when handling.
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4
NCP5359A
ELECTRICAL CHARACTERISTICS
(V
CC
= 10 V
−
13.2 V, T
A
= 0°C to +85°C, V
EN
= 5 V unless otherwise noted)
Characteristics
Supply Voltage
V
CC
Operating Voltage
Power ON Reset threshold
Supply Current
V
CC
Quiescent Supply Current in Normal
Operation
V
CC
Standby Current
BST Quiescent Supply Current in Normal
Operation
BST Standby Current
Undervoltage Lockout
V
CC
Start Threshold
V
CC
UVLO Hysteresis
Output Overvoltage Trip Threshold at
Startup
EN Input
Input Voltage High
Input Voltage Low
Hysteresis (Note 4)
Enable Pin Sink Current
Propagation Delay Time (Note 4)
PWM Input
DRVH Comparator Drop Threshold
PWM Input Self Bias Voltage
DRVL Comparator Rise Threshold
Input Current
High Side Driver
Output Resistance, Sourcing
Output Resistance, Sinking
Output Resistance, unbiased (Note 4)
SW Pull Down Resistance (Note 4)
Transition Time (Note 6)
Propagation Delay (Notes 4 & 5)
Low Side Driver
Output Resistance, Sourcing
Output Resistance, Sinking
Output Resistance, unbiased (Note 4)
Transition Time (Note 6)
Propagation Delay (Notes 4 & 5)
Negative Current Detector Threshold
Thermal Shutdown
Thermal Shutdown
Thermal Shutdown Hysteresis
Tsd
Tsd
hys
(Note 6)
(Note 6)
150
170
20
°C
°C
tr
DRVL
tf
DRVL
tpdh
DRVL
tpdl
DRVL
V
NCDT
R
H_BG
R
L_BG
SW = GND
SW = V
CC
BST
−
SW = 0 V
C
LOAD
= 3 nF
C
LOAD
= 3 nF
Driving High, C
LOAD
= 3 nF
Driving Low, C
LOAD
= 3 nF
(Note 6)
10
15
−1.0
10
16
15
2.0
1.0
3.5
2.5
55
25
20
35
35
mV
ns
W
W
kW
ns
tr
DRVH
tf
DRVH
tpdh
DRVH
tpdl
DRVH
R
H_TG
R
L_TG
V
BST
– V
SW
= 12 V
V
BST
– V
SW
= 12 V
BST
−
SW = 0 V
SW to GND
C
LOAD
= 3 nF, V
BST
– V
SW
= 12 V
C
LOAD
= 3 nF, V
BST
– V
SW
= 12 V
Driving High, C
LOAD
= 3 nF
Driving Low, C
LOAD
= 3 nF
10
15
10
10
16
15
2.0
1.0
3.5
2.5
55
55
25
20
35
30
ns
W
W
kW
kW
ns
VTH_DRVH
V
PWM
VTH_DRVL
I
PWM
PWM = 0 V, EN = GND
30
2.2
1.4
1.5
1.6
0.8
V
V
V
mA
V
EN_HI
V
EN_LOW
V
EN_HYS
I
EN_SINK
tpd
hEN
tpd
lEN
V
CC
= 5.5 V
4.0
20
20
60
60
500
2.0
1.0
V
V
mV
mA
ns
ns
VCC
TH
VCC
HYS
OVPSU
Power Startup time, V
CC
> 9 V.
(Without trimming)
1.8
8.2
8.7
1.0
2.0
9.5
V
V
V
I
VCC_NORM
I
VCC_SBC
I
BST1_normal
I
BST2_normal
I
BST1_SD
I
BST2_SD
EN = 5 V, PWM = OSC, F
SW
= 100 k
C
LOAD
= 0 p
EN = GND; No switching
PWM = +5 V, SW = 0 V
PWM = GND, SW = 0 V
PWM = +5 V
PWM = GND
5.0
0.5
1.0
1.0
0.25
0.25
8.0
2.5
1.8
1.8
mA
mA
mA
mA
V
CC
V
POR
10
2.8
13.2
V
V
Symbol
Test Conditions
Min
Typ
Max
Units
4. Guaranteed by design; not tested in production .
5. For propagation delays, ”t
pdh
” refers to the specified signal going high ”t
pdl
” refers to it going low.
6. Design guaranteed.
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5
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