V54C3512804VK
512Mbit SDRAM, 3.3 VOLT
64M X 8
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
75
133 MHz
7.5 ns
5.4 ns
6 ns
Features
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Description
The V54C3512804VK is a four bank Synchro-
nous DRAM organized as 4 banks x 16Mbit x 8. The
V54C3512804VK achieves high speed data trans-
fer rates up to 143 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
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4 banks x 16Mbit x 8 organization
High speed data transfer rates up to 143 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II(V54C3512804VKI)
Available in 54 Ball FBGA (V54C3512804VKK)
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
Package Out-
line
54 Pin TSOP II
54 Ball FBGA
•
•
6
•
•
Access Time (ns)
7
•
•
75
•
•
Power
Std.
•
•
Temperature
Mark
Blank
I
V54C3512804VK Rev. 1.2 January 2020
1
ProMOS TECHNOLOGIES
Capacitance*
(at Ta=0 to 25 °C, V
CC
= V
CCQ
= 3.3 V ± 0.3 V)
Parameter
Input Capacitance: CLK
Symbol
Min. Max. Unit
C
CLK
2.5
2.5
4
3.5
3.8
6
pF
pF
pF
V54C3512804VK
Absolute Maximum Ratings*
Operating temperature range ..........0 to 70 °C for normal
-40 to 85 °C for Industrial
Storage temperature range .........................-55 to 150 °C
Input/output voltage ........................... -0.3 to (V
CC
+0.3) V
Power supply voltage ................................... -0.3 to 4.6 V
Power dissipation ...................................................... 1 W
Data out current (short circuit) ............................... 50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Input Capacitance: All other input C
IN
pins and balls
Input/output Capacitance: DQ
C
IO
*Note:Capacitance is sampled and not 100% tested.
V54C3512804VK Rev1.2 January 2020
5
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