V54C3256324VK
256Mbit SDRAM, 3.3 VOLT
8M X 32
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
6.5 ns
7
143 MHz
7 ns
5.4 ns
6.5 ns
75
133 MHz
7.5 ns
-
6 ns
Features
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Description
The V54C3256324VK is a four bank Synchro-
nous DRAM organized as 4 banks x 2Mbit x 32. The
V54C3256324VK achieves high speed data trans-
fer rates up to 166 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
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4 banks x 2Mbit x 32 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 86-Pin TSOPII and 90-Ball FBGA
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
Package Outline
86L TSOP
90B FBGA
•
•
Access Time (ns)
6
•
•
Power
75
•
•
7
•
•
Std.
•
•
Temperature
Mark
Blank
I
V54C3256324VK Rev. 1.0 October 2015
1
ProMOS TECHNOLOGIES
Capacitance*
VDD=VDDQ=3.3V, TA=25°C, f=1MHz, pin under test biased at 1.4V.
V54C3256324VK
Absolute Maximum Ratings*
Operating temperature range ......................0 to 70°C for normal
-40 to 85 °C for industrial
Storage temperature range ....................................-55 to 125 °C
Input/output voltage ...................................... -0.3 to (V
CC
+0.3) V
Power supply voltage .............................................. -1.0 to 4.6 V
Power dissipation ..................................................................1 W
Data out current (short circuit) ...........................................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol Parameter
C
IN1
C
IN2
C
IO
Input Capacitance (CLK)
Input Capacitance (All other input pins )
Data Input/Output Capacitance (I/O)
Max. Unit
4
4
6
pF
pF
pF
*Note:Capacitance is sampled and not 100% tested.
Block Diagram
x32 Configuration
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
4096 x 512
x 32 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 512
x 32 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 512
x 32 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 512
x 32 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
32
DQM0~3
CKE
RAS
CLK
CAS
WE
CS
V54C3256324VK Rev. 1.0 October 2015
5
单片机
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