V55C2256164VG
256Mbit MOBILE SDRAM
2.5 VOLT FBGA PACKAGE 16M X 16
7
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
Clock Access Time (t
AC1
) CAS Latency = 1
143 MHz
7 ns
5.4 ns
6 ns
19 ns
8PC
125 MHz
8 ns
6 ns
6 ns
19 ns
10
100MHz
10 ns
7 ns
8 ns
22 ns
Features
■
4 banks x 4Mbit x 16 organization
■
High speed data transfer rates up to 143 MHz
■
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■
Single Pulsed RAS Interface
■
Data Mask for Read/Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency:1, 2, 3
■
Programmable Wrap Sequence: Sequential or
Interleave
■
Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■
Multiple Burst Read with Single Write Operation
■
Automatic and Controlled Precharge Command
■
Random Column Address every CLK (1-N Rule)
■
Power Down Mode and Clock Suspend Mode
■
Deep Power Down Mode
■
Auto Refresh and Self Refresh
■
Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■
■
■
■
Available in 54-ball FBGA, with 9x6 ball array
with 3 depupulated rows, 8x10 mm and 54 pin
TSOP II
■
VDD=2.5V, VDDQ=2.5V
■
Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■
Drive Strength (DS) option: Full, 1/2, 1/4 and 1/8
■
Refresh Interval:
8192 cycles/64ms [0 to 70
o
C (Commercial)];
8192 cycles/64ms [-40 to 85
o
C (Industrial)];
8192 cycles/32ms [-40 to 105
o
C (H)];
8192 cycles/32ms [-40 to 125
o
C (Extended)]
■
Operating Temperature Range
Commercial (0°C to 70°C)
Industrial (-40°C to +85°C)
■
H-grade (-40°C to +105°C)
■
Extended (-40
o
C to +125
o
C)
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
-40
o
to +105
o
C
-40
o
to +125
o
C
Package Outline
C/T
•
•
•
•
Access Time (ns)
7
•
•
•
•
8PC
•
•
•
•
10
•
•
•
•
Temperature
Mark
Commercial
Industrial
H
E
V55C2256164VG Rev. 1.0 September 2008
1
ProMOS TECHNOLOGIES
Part Number Information
V55C2256164VG
V
ProMOS
5 5
C
2
2 5 6 1 6
ORGANIZATION
& REFRESH
1Mx16, 2K : 1616
4Mx16, 4K : 6516
4
V
G
K
7
OTHER
PC
: CL2
TYPE
54 : SDRAM
55 : MOBILE SDRAM
32Mx4, 4K : 12840
16Mx8, 4K : 12880
64Mx4, 8K : 25640
32Mx8, 8K : 25680
128Mx4, 8K : 51240
64Mx8, 8K : 51280
8Mx16, 4K : 12816
BLANK: CL3
TEMPERATURE
BLANK: 0 - 70C
16Mx16, 8K : 25616
32Mx16, 8K : 51216
I:
H:
E:
-40 - 85C
-40 - 105C
-40 - 125C
7 : 143MHz
6 : 166MHz
5 : 200MHz
CMOS
BANKS
VOLTAGE
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
REV LEVEL
A: 1st
B: 2nd
G: 7th
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
C: 3rd
D: 4th
PACKAGE
LEAD
PLATING
T
S
C
B
D
Z
R
E
F
G
H
RoHS
I/O
V: LVTTL
SPEED
10 : 100MHz
8 : 125MHz
75 : 133MHz
4:
3:
2:
1:
3.0V
3.3 V
2.5 V
1.8 V
GREEN PACKAGE
DESCRIPTION
I
J
K
M
N
P
TSOP
60-Ball FBGA
54-BallFBGA
BGA
Die-stacked TSOP
Die-stacked FBGA
* RoHS: Restriction of Hazardous Substances
* Green: RoHS-compliant and Halogen-free
V55C2256164VG Rev. 1.0 September 2008
2
ProMOS TECHNOLOGIES
V55C2256164VG
Description
FBGA
Pkg.
C
Pin Count
54
60 Pin WBGA PIN CONFIGURATION
Top View
Pin Configuration for x16 devices:
1
2
3
A
B
C
D
E
F
G
H
J
7
8
9
VDD
DQ1
DQ3
DQ5
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8
NC
VSS
CKE
A9
A6
A4
VDDQ DQ0
VSSQ DQ2
VDDQ DQ4
VSSQ DQ6
VDD LDQM DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
UDQM CLK
A12
A8
VSS
A11
A7
A5
< Top-view >
V55C2256164VG Rev.1.0 September 2008
3
ProMOS TECHNOLOGIES
V55C2256164VG
Description
TSOP-II
Pkg.
T
Pin Count
54
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+2.5V)
Ground
Power for I/O’s (+2.5V)
Ground for I/O’s
Not connected
V
CC
I/O
1
V
CCQ
I/O
2
I/O
3
V
SSQ
I/O
4
I/O
5
V
CCQ
I/O
6
I/O
7
V
SSQ
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
V
SS
I/O
16
V
SSQ
I/O
15
I/O
14
V
CCQ
I/O
13
I/O
12
V
SSQ
I/O
11
I/O
10
V
CCQ
I/O
9
V
SS
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
CS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
16
LDQM, UDQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V55C2256164VG Rev. 1.0 September 2008
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ProMOS TECHNOLOGIES
Description
V55C2256164VG
The V55C2256164VG is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The
V55C2256164VG achieves high speed data transfer rates up to 143 MHz by employing a chip architecture
that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-
ternally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Signal Pin Description
Pin
CLK
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 16M x 16 SDRAM CA0–CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
CS
Input
Pulse
RAS, CAS
WE
A0 - A12
Input
Pulse
Input
Level
BA0,
BA1
DQx
Input
Level
—
Selects which bank is to be active.
Input
Output
Input
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM
UDQM
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
Power and ground for the input buffers and the core logic.
VCC, VSS
VCCQ
VSSQ
Supply
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V55C2256164VG Rev. 1.0 September 2008
5
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