Bi-directional pin. Upon power-on, the value of VDD_SEL is latched in and used to
select the power (see Power Selection table 2 ). Internal pull down defaults SST1 to 0,
use external pull-up to set to 1. After power-up this pin acts as 12MHz output clock.
Bi-directional and Tri-level pin. Upon power-on, the value of SEL10_8 is latched in and
used to select the output frequency (See frequency selection table 3 ). Tri level input: M
= Do not connect, 1 = Pull up, 0 = Pull down. After power-up this pin acts as 10MHz
clock, 8MHz clock, or “No output”, depending on SEL10_8.
Ground connection.
Bi-directional pin. Upon power-on, the value of XTAL_SEL is latched in and used to set
the input crystal frequency (24.575MHz or 14.31818MHz). Set XTAL_SEL to 0 (default)
for 24.576MHz input crystal, set XTAL_SEL to 1 for 14.31818MHz input crystal (see
Crystal Selection Table on page 1). . After power-up this pin acts as 27MHz output
(with 24.576MHz crystal) or as 14.31818MHz pass through clock (with 14.31818MHz
crystal), depending on the input crystal.
The 27MHz output can be modulated for low EMI using Spread Spectrum.
3.3V power supply for 27MHz, 10MHz, 12MHz, and 24.576MHz.
24.576MHz/SST1
VDDB1
VDD25M
25MHzx2
VSS25M
12MHz/VDD_SEL
7
8
9
10
11
12
B
P
P
O
P
B
10_8MHz/SEL10_8
VSSB2
13
14
B
P
27_14.318MHz/XTAL_SEL
15
B
VDDB2
16
P
FUNCTIONAL DESCRIPTION
Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-02 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =
Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are
in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to
GND. Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/30/05 Page 3
PLL702-02
Low EMI Peripheral Clock Generator for Notebook & Motherboards
Connecting a bi-directional pin
The PLL702-02 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs
have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can
be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in
order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-
up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin
and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-
directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up
resistor.
Note:
when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor
may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the
pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram).
Note:
when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is
in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be
dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is particularly
true when driving 74FXX TTL components.
APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP
Internal to chip
VDD
External Circuitry
R
up
Power Up
Reset
R
RB
Output
EN
Bi-directional pin
Clock Load
Latched
Input
Latch
R
UP
/
4
Jumper options
NOTE:
Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/30/05 Page 4
PLL702-02
Low EMI Peripheral Clock Generator for Notebook & Motherboards
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications
PARAMETERS
Input Frequency (to be set via XTAL_SEL)
Output Rise Time
Output Fall Time
Duty Cycle
Duty Cycle 8MHz clock
Max. Absolute Period Jitter
Max. Jitter, cycle to cycle
CONDITIONS
+/- 20ppm accuracy
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
At VDD/2
Long term, No SST
Long term + Short term
MIN.
TYP.
14.31818
24.576
MAX.
UNITS
MHz
MHz
1.5
1.5
45
43
50
50
55
57
150
120
ns
ns
%
%
ps
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
FPGA/CPLD
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