Model 635
Low Jitter LVPECL or LVDS Clock
Features
Ceramic Surface Mount Package
Low Phase Jitter Performance, 700fs Maximum
Fundamental or 3
rd
Overtone Crystal Design
Frequency Range 10 – 320MHz *
+2.5V or +3.3V Operation
Output Enable Standard
Tape and Reel Packaging, EIA‐418
Part Dimensions:
7.0 × 5.0 × 2.0mm • 178.462mg
Applications
SerDes
Storage Area Networking
Broadband Access
SONET/SDH/DWDM
PON
Ethernet/GbE/SyncE
Fiber Channel
Test and Measurement
Standard Frequencies
‐ 25.00MHz
‐ 50.00MHz
‐ 100.00MHz
‐ 125.00MHz
‐ 155.52MHz
‐ 156.25MHz
‐ 161.1328MHz
‐ 187.50MHz
‐ 200.00MHz
‐ 212.50MHz
‐ 250.00MHz
‐ 312.50MHz
* Check with factory for availability.
Description
CTS Model 635 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.
Employing the latest IC technology, M635 has excellent stability and low jitter/phase noise performance.
Ordering Information
Model
635
P
Output Type
Frequency
Stability
3
Temperature
Range
I
Supply
Voltage
3
Frequency Code
[MHz]
XXXMXXXX
Code
P
L
E
V
Output
LVPECL ‐ Pin 1 Enable
LVDS ‐ Pin 1 Enable
LVPECL ‐ Pin 2 Enable
LVDS ‐ Pin 2 Enable
Code Temp. Range
‐10°C to +60°C
A
‐20°C to +70°C
C
‐40°C to +85°C
I
Code
Frequency
2
Product Frequency Code
Code
6
5
3
2
Stability
±20ppm
±25ppm
±50ppm
±100ppm
1
Code
2
3
Voltage
+2.5Vdc
+3.3Vdc
Notes:
1] Consult factory for availability of 6I Stability/Temperature combination.
2] Frequency is recorded with 3 significant digits before the 'M' and 4 significant digits after the 'M',
including zeros. See Table I for frequency codes that exceed 4 significant digits.
Table I
Nominal Freq uenc y
P art Nu mb er
[MHz]
Freq uenc y Cod e
025.000625
025M0006
074.175824
074M175B
101.575694
101M5756
125.009375
125M0093
148.351648
148M351A
153.600770
153M6007
156.253906
156M2539
178.018970
178M0189
Example: P/N Frequency = Actual Frequency.
148M351A = 148.351648MHz
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
Page 1 of 7
DOC# 008‐0284‐0 Rev. F
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 635
Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Operating Conditions
P
ARAMETER
Maximu
m Supply Voltage
Supp
ly Vo ltage
Supp
ly Cu rrent
LVP
ECL
LVDS
O
perating Temperatu re
Storage Temperature
T
A
T
STG
‐
‐
I
CC
Maximum Load
‐
‐
‐20
‐40
‐40
55
45
+25
‐
88
66
+70
+85
+125
mA
SYMBO L
V
CC
V
CC
CO NDITIO NS
‐
±5%
MIN
‐0.5
2.375
3.135
TYP
‐
2.5
3.3
MAX
5.0
2.625
3.465
UNIT
V
V
°C
°C
Frequency Stability
P
ARAMETER
Frequenc
y
Range
LVP
ECL
LVDS
Frequenc
y
Stability
[Note 1]
SYMBO L
f
O
CO NDITIO NS
‐
MIN
TYP
10 ‐ 320
80 ‐ 320
MAX
UNIT
MHz
±ppm
3
ppm
Δf/f
O
Δf/f
25
‐
First Year @ +25°C, nominal V
CC
‐3
20, 25, 50 or 100
‐
Aging
1.] Inc lusive of initial toleranc e at time of shipment, c hanges in supply voltage, load, temperature and 1st year aging.
Output Parameters
P
ARAMETER
O
utp ut Ty pe
O
utp ut Lo ad
SYMBO L
‐
R
L
V
OH
O
utp ut Voltage Lev els
V
OL
V
OH
V
OL
O
utp ut Du ty Cy c le
Rise and Fall Time
SYM
T
R
, T
F
CO NDITIO NS
‐
Terminated to V
CC
‐ 2.0V
PECL Load, ‐20°C to +70°C
‐
V
CC
‐ 1.025
V
CC
‐ 1.810
V
CC
‐ 1.085
V
CC
‐ 1.830
45
‐
MIN
TYP
LVPECL
50
‐
‐
‐
‐
‐
0.3
LVDS
‐
‐
0.90
45
247
1.125
‐
100
1.43
1.10
‐
330
1.25
0.4
‐
1.60
‐
55
454
1.375
0.7
‐
V
CC
‐ 0.880
V
CC
‐ 1.620
V
CC
‐ 0.880
V
CC
‐ 1.555
55
0.7
MAX
UNIT
‐
Ohms
V
PECL Load, ‐40°C to +85°C
@ V
CC
‐ 1.3V
@ 20%/80% Levels, R
L
= 50 Ohms
V
%
ns
O
utp ut Ty pe
O
utp ut Lo ad
O
utp ut Voltage Lev els
O
utp ut Du ty Cy c le
Differential O
utpu t Voltage
O
ffset Voltage
Rise and Fall Time
‐
R
L
V
OH
V
OL
SYM
V
OD
V
OS
T
R
, T
F
‐
Between Outputs
LVDS Load
@ 1.25V
R
L
= 100 Ohms
LVDS Load
@ 20%/80% Levels, R
L
= 100 Ohms
‐
Ohms
V
%
mV
V
ns
DOC# 008‐0284‐0 Rev. F
Page 2 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 635
Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Output Parameters
P
ARAMETER
Start Up Time
Enable Func
tion [Standby ]
Enable Input Voltage
Disable Input Voltage
Disable Time
Enable Time
P
hase Jitter, RMS
P
eriod Jitter, pk‐pk
P
eriod Jitter, RMS
V
IH
V
IL
T
PLZ
T
PLZ
tjrms
pjpk‐pk
pjrms
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
Bandwidth 12 kHz ‐ 20 MHz
‐
‐
0.7V
CC
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
300
2.6
25
‐
0.3V
CC
200
2
700
‐
‐
V
V
ns
ms
fs
ps
ps
SYMBO L
T
S
CO NDITIO NS
Application of V
CC
MIN
‐
TYP
2
MAX
5
UNIT
ms
Enable Truth Table
Pin 1 or Pin 2
Logic ‘1’
Open
Logic ‘0’
Pin 4 & Pin 5
Output
Output
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008‐0284‐0 Rev. F
Page 3 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 635
Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
25MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
100MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
DOC# 008‐0284‐0 Rev. F
Page 4 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 635
Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
155.52MHz, LVDS, V
CC
= 3.3V, T
A
= +25°C
Phase Noise Tabulated
Typical, V
CC
= 3.3V, T
A
= +25°C
P
ARAMETER
LVP ECL @
2
5 .0 0 MHz
P
h ase No ise
Single Side Band
@ 10Hz
@ 100Hz
‐
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
P
h ase Jitter, RMS
tjrms
‐75.14
‐112.50
‐142.15
‐155.01
‐159.99
‐161.83
‐161.61
fs
P
hase Jitter, RMS
tjrms
dBc/Hz
‐
SYMBO L
CO NDITIO NS
TYP
UNIT
P
ARAMETER
LVP ECL @
1
0 0 .0 0 MHz
P
hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
‐65.65
‐100.19
‐131.02
‐145.49
‐150.36
‐151.37
‐152.11
fs
dBc/Hz
SYMBO L
CO NDITIO NS
TYP
UNIT
Integration Bandwidth 12kHz ‐ 20MHz
179.24
Integration Bandwidth 12kHz ‐ 20MHz
132.20
P
ARAMETER
LVDS @
1
5 5 .5 2 MHz
P
h ase No ise
SYMBO L
CO NDITIO NS
TYP
UNIT
Single Side Band
@ 10Hz
@ 100Hz
‐
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 20MHz
‐69.89
‐103.42
‐130.99
‐142.69
‐144.46
‐144.49
‐145.13
fs
dBc/Hz
P
h ase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz
383.70
DOC# 008‐0284‐0 Rev. F
Page 5 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
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