feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
1
) and write enable (WE) inputs LOW and chip enable
two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
16
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128 is available in a standard 400-mil-wide SOJ,
525-mil wide (450-mil-wide body width) SOIC and 32-pin
TSOP type I.
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
Logic Block Diagram
Pin Configurations
Top View
SOJ / SOIC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
I/O
2
512 x 256 x 8
ARRAY
I/O
3
I/O
4
I/O
5
POWER
DOWN
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CE
1
CE
2
WE
OE
COLUMN
DECODER
I/O
6
I/O
7
62128-1
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
62128-2
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
July 1996 - Revised November 1996
PRELIMINARY
Selection Guide
CY62128–55
Maximum Access Time (ns)
Maximum Operating Current
Commercial
L
LL
Maximum CMOS Standby Current
Commercial
L
LL
55
115 mA
70 mA
70 mA
10 mA
100
µA
20
µA
CY62128
CY62128–70
70
110 mA
60 mA
60 mA
10 mA
100
µA
20
µA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
.....................................–0.5V to V
CC
+0.5V
DC Input Voltage
[1]
..................................–0.5V to V
CC
+0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[2]
0°C to +70°C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
62128–55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output Disabled
Com’l
L
LL
I
SB1
Automatic CE
Power-Down Current
— TTL Inputs
Automatic CE
Power-Down Current
— CMOS Inputs
Max. V
CC
, CE
1
≥
V
IH
or CE
2
< V
IL
,
V
IN
≥
V
IH
or
V
IN
≤
V
IL
, f = f
MAX
Max. V
CC
,
CE
1
≥
V
CC
– 0.3V,
or CE
2
≤
0.3V,
V
IN
≥
V
CC
– 0.3V,
or V
IN
≤
0.3V, f=0
Com’l
L
LL
Com’l
L
LL
Test Conditions
V
CC
= Min., I
OH
= – 1.0 mA
V
CC
= Min., I
OL
= 2.1mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+5
–300
115
70
70
25
10
2
10
100
20
2.2
–0.3
–1
–5
Max.
62128–70
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+5
–300
110
60
60
25
10
2
10
100
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
Output Short Circuit Current
[4]
V
CC
= Max., V
OUT
= GND
V
CC
Operating
V
CC
= Max.
,
Supply Current
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
I
SB2
Shaded areas contain advance information
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
PRELIMINARY
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
9
9
CY62128
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R1 1800
Ω
R1 1800
Ω
5V
OUTPUT
R2
990
Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
990
Ω
GND
≤
5ns
3.0V
90%
10%
90%
10%
≤
5 ns
ALL INPUT PULSES
62128-3
62128-4
THÉVENIN EQUIVALENT
639
Ω
1.77V
OUTPUT
Switching Characteristics
[3,6]
Over the Operating Range
62128–55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7, 8]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[8]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[7, 8]
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
CE
1
HIGH to Power-Down, CE
2
LOW to Power-Down
Write Cycle Time
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
55
45
45
0
0
45
45
0
55
70
60
60
0
0
50
55
5
20
0
70
0
20
5
25
5
55
20
0
25
55
55
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
62128–70
Min.
Max.
Unit
WRITE CYCLE
[9]
Shaded areas contain advance information
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100pF load capacitance.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
3
PRELIMINARY
Switching Characteristics
[3,6]
Over the Operating Range (continued)
62128–55
Parameter
t
HD
t
LZWE
t
HZWE
WE HIGH to Low Z
[8]
WE LOW to High Z
[7,8]
Description
Data Hold from Write End
Min.
0
5
20
Max.
CY62128
62128–70
Min.
0
5
25
Max.
Unit
ns
ns
ns
Shaded area contains advanced information.
Switching Waveforms
Read Cycle No.1
[10,11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
[11,12]
DATA VALID
62128-5
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZCE
DATA VALID
t
PD
50%
ISB
62128-6
HIGH
IMPEDANCE
ICC
Notes:
10. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
4
PRELIMINARY
Switching Waveforms
(continued)
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[13,14]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
t
HD
t
HA
CY62128
62128-7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[13,14]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 15
t
HZOE
Notes:
13. Data I/O is high impedance if OE = V
IH
.
14. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
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