74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Rev. 5 — 25 November 2010
Product data sheet
1. General description
The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry
and an output from each of the eight stages. Data is entered serially through one of two
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry
through the other input. Both inputs must be connected together or an unused input must
be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input
and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
2. Features and benefits
Input levels:
For 74HC164: CMOS level
For 74HCT164: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.
NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC164N
74HCT164N
74HC164D
74HCT164D
74HC164DB
74HCT164DB
74HC164PW
74HCT164PW
74HC164BQ
74HCT164BQ
40 C
to +125
C
DHVQFN14
40 C
to +125
C
TSSOP14
40 C
to +125
C
SSOP14
40 C
to +125
C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT337-1
SOT402-1
40 C
to +125
C
Name
DIP14
Description
plastic dual in-line package; 14 leads (300 mil)
Version
SOT27-1
Type number
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
SRG8
8
9
1
2
C1/
R
3
4
&
1D
DSA
DSB
3
1
2
4
5
6
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac424
5
6
10
11
12
13
CP
MR
8
9
11
12
13
001aac423
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
DSA
DSB
CP
MR
1
2
8
9
3
4
5
6
10
11
12
13
8-BIT SERIAL−IN/PARALLEL−OUT
SHIFT REGISTER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac425
Fig 3.
74HC_HCT164
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 25 November 2010
2 of 20
NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
DSA
D
DSB
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac616
Fig 4.
Functional diagram
5. Pinning information
5.1 Pinning
74HC164
74HCT164
DSA
2
3
4
5
6
7
GND
CP
8
GND
(1)
1
terminal 1
index area
DSB
14 V
CC
13 Q7
12 Q6
11 Q5
10 Q4
9
8
001aal390
74HC164
74HCT164
DSA
DSB
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
14 V
CC
13 Q7
12 Q6
11 Q5
10 Q4
9
MR
Q0
Q1
Q2
Q3
MR
CP
001aal391
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration DIP14, SO14, (T)SSOP14
Fig 6.
Pin configuration DHVQFN14
74HC_HCT164
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 25 November 2010
3 of 20
NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
5.2 Pin description
Table 2.
Symbol
DSA
DSB
Q0 to Q7
GND
CP
MR
V
CC
Pin description
Pin
1
2
3, 4, 5, 6, 10, 11, 12, 13
7
8
9
14
Description
data input
data input
output
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
positive supply voltage
6. Functional description
Table 3.
Operating
modes
Reset (clear)
Shift
Function table
[1]
Input
MR
L
H
H
H
H
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
Output
CP
X
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Conditions
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
50
-
+150
Unit
V
mA
mA
mA
mA
mA
C
74HC_HCT164
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 25 November 2010
4 of 20
NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Table 4.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
P
tot
Parameter
total power dissipation
DIP14 package
SO14, (T)SSOP14 and
DHVQFN14 packages
[1]
[2]
Conditions
[2]
Min
-
-
Max
750
500
Unit
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC164
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT164
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC164
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT164
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 25 November 2010
5 of 20
MEMS传感器
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