CY7C1345G
4 Mbit (128K x 36) Flow Through Sync
SRAM
Features
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Functional Description
The CY7C1345G is a 128K x 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining Chip Enable (CE
1
), depth expansion
Chip Enables (CE
2
and CE
3
), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW
x
, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3V core power supply
while all outputs operate with either a +2.5 or +3.3V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines.
128K x 36 common I/O
3.3V core Power Supply (V
DD
)
2.5V or 3.3V I/O Supply (V
DDQ
)
Fast Clock-to-output times
❐
6.5 ns (133 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel Pentium
interleaved or Linear Burst Sequences
Separate Processor and Controller Address Strobes
Synchronous Self Timed Write
Asynchronous output enable
Available in Pb-free 100-Pin TQFP package, Pb-free and
non-Pb-free 119-Ball BGA package
ZZ Sleep Mode option
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
133 MHz
6.5
225
40
100 MHz
8.0
205
40
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 38-05517 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 27, 2009
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CY7C1345G
Pin Definitions
Name
A0, A1, A
I/O
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input Clock
Input
Synchronous
Input
Synchronous
Input
Synchronous
Description
Address Inputs Used to Select One of the 128K Address Locations.
Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed
the two bit counter.
Byte Write Select Inputs, Active LOW.
Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW.
When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
Byte Write Enable Input, Active LOW.
Sampled on the rising edge of CLK. This signal is asserted
LOW to conduct a byte write.
Clock Input.
Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only
when a new external address is loaded.
Chip Enable 2 Input, Active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select or deselect the device. CE
2
is sampled only when a new external address is
loaded.
Chip Enable 3 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
2
to select or deselect the device. CE
3
is sampled only when a new external address is
loaded.
BW
A,
BW
B
BW
C
, BW
D
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
Input
Output Enable, Asynchronous Input, Active LOW.
Controls the direction of the IO pins. When
Asynchronous LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tristated and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input
Synchronous
Input
Synchronous
Advance Input Signal,
Sampled on the Rising Edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When
asserted LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When
asserted LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized.
ADV
ADSP
ADSC
Input
Synchronous
ZZ
Input
ZZ sleep Input, Active HIGH.
When asserted HIGH places the device in a non-time critical sleep
Asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
has an internal pull down.
IO
Synchronous
Bidirectional Data IO lines.
As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the pins
is controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and
DQP
[A:D]
are placed in a tristate condition.
DQs
DQP
A,
DQP
B
DQP
C,
DQP
D
V
DD
V
SS
V
DDQ
V
SSQ
Power Supply
Power Supply Inputs to the Core of the Device.
Ground
IO Power
Supply
IO Ground
Ground for the Core of the Device.
Power Supply for the IO Circuitry.
Ground for the IO circuitry.
Document Number: 38-05517 Rev. *F
Page 5 of 21
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