HI-8683, HI-8684
January 2001
ARINC INTERFACE DEVICE
ARINC 429 & 561 Serial Data to 8-Bit Parallel Data
PIN CONFIGURATIONS
(Top View)
DESCRIPTION
The HI-8683 and HI-8684 are system components for
interfacing incoming ARINC 429 signals to 8-bit parallel
data using proven +5V analog/digital CMOS technology.
The HI-8683 is a digital device that requires an external
analog line receiver such as the HI-8482 or HI-8588
between the ARINC bus and the device inputs. The HI-8684
incorporates the digital logic and analog line receiver
circuitry in a single device.
The HI-8683 is also available as a second source to the
DLS-112 with the original 18 pin DIP and 28 pin PLCC
package pinouts.
The receivers on the HI-8684 connect directly to the ARINC
429 Bus and translate the incoming signals to normal CMOS
levels. Internal comparator levels are set just below the
standard 6.5 volt minimum data threshold and just above the
standard 2.5 volt maximum null threshold. The -10 version
of the HI-8684 allows the incorporation of an external 10K
Ω
resistance in series with each ARINC input for lightning
protection without affecting ARINC level detection.
Both products offer high speed 8-bit parallel bus interface, a
32-bit buffer, and error detection for word length and parity.
A reset pin is also provided for power-on initialization.
DATARDY
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
18
17
16
15
Vcc
GAPCLK
RESET
INB
INA
ERROR
PARITY ENB
READ
GND
HI-8683PSI
HI-8683PST
14
13
12
11
10
HI-8683
18-Pin Plastic SOIC - WB Package
Vcc
1
2
3
4
5
6
7
8
9
10
20
19
18
GAPCLK
TESTA
TESTB
RESET
RINB (-10)
RINA (-10)
ERROR
PARITY ENB
READ
GND
FEATURES
!
Automatic conversion of serial ARINC 429, 575 &
561 data to 8-bit parallel data
DATARDY
D7
D6
D5
D4
D3
D2
D1
D0
!
High speed parallel 8-bit data bus
!
Error detection - word length and parity
!
Reset input for power-on initialization
!
On-chip line receiver option (HI-8684)
!
Input hysteresis of at least 2 volts (HI-8684)
!
Test inputs bypass analog inputs (HI-8684)
!
Simplified lightning protection with the ability to add
10 Kohm external series resistors (HI-8684-10)
PLCC and DIP
HI-8684PSI
HI-8684PST
&
HI-8684PSI-10
HI-8684PST-10
17
16
15
14
13
12
11
HI-8684
20-Pin Plastic SOIC - WB Package
(See page 8 for additional pin configurations)
!
Plastic package options - surface mount (SOIC),
!
Military processing available
HOLT INTEGRATED CIRCUITS
1
(DS8683 Rev. D)
01/01
HI-8683, HI-8684
PIN DESCRIPTIONS
SIGNAL
DATA RDY
D1 to D7
GND
READ
PARITY ENB
ERROR
FUNCTION
OUTPUT
OUTPUT
POWER
INPUT
INPUT
OUTPUT
DESCRIPTION
Receiver data ready flag. A high level indicates data is available in the receive
buffer. Flag goes low when the first 8-bit byte is read.
8-bit parallel data bus (tri-state)
0V
Read strobe. A low level transfers receive buffer data to the data bus
Parity Enable - A high level activates odd parity checking which replaces the
32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged
Error Flag. A high level indicates a bit count error (number of ARINC bits was
less than or greater than 32) and/or a parity error if parity detection was enabled
(PARITY ENB high)
Positive digital serial data input (HI-8683 only)
Negative digital serial data input (HI-8683 only)
Positive direct ARINC serial data input (HI-8684 & HI-8684-10 only)
Negative direct ARINC serial data input (HI-8684 & HI-8684-10 only)
Internal logic states are initialized with a low level
Used in conjunction with the TESTB input to bypass the built-in analog line
receiver circuitry (HI-8684 & HI-8684-10 only)
Used in conjunction with the TESTA input to bypass the built-in analog line
receiver circuitry (HI-8684 & HI-8684-10 only)
Gap Clock. Determines the minimum time required between ARINC words for
detection. The minimum word gap time is between 16 and 17 clock cycles of
this signal.
+5V ±10% supply
INA
INB
RINA/RINA-10
RINB/RINB-10
RESET
TESTA
TESTB
GAPCLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Vcc
POWER
FUNCTIONAL DESCRIPTION
The HI-8683 and HI-8684 are serial to 8-bit parallel convert-
ers. The incoming data stream is serially shifted into an input
register, checked for errors, and then transferred in parallel to
a 32-bit receive buffer. The receive data can be accessed us-
ing four 8-bit parallel read operations while the next serial
data steam is being received.
RECEIVER INPUTS
Figure 1 is a block diagram of both the HI-8683 and HI-8684.
The difference between the two products is the HI-8684 has
a built-in line receiver whereas the HI-8683 is strictly a digital
device and requires an external ARINC line receiver such as
the Holt HI-8482, HI-8588 or HI-8590 to interface to the
ARINC 429 bus.
HI-8684 Line Receiver
Typically 35K
Ω
resistors are in series with both the RINA and
RINB ARINC 429 inputs. They connect to level translators
whose resistance to GND is typically 10K
Ω.
After level trans-
lation, the buffered inputs drive a differential amplifier. The
differential signal is compared to levels derived from a divider
between VCC and GND. The nominal settings correspond to
a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A
valid ARINC One/Zero input sets a latch and a Null input re-
sets the latch.
Since any added external series resistance will affect the volt-
age translation, the HI-8684-10 is available with 25K
Ω
of the
35K
Ω
series resistance required for proper ARINC 429 level
detection. The remaining 10K
Ω
required that must be added
can be incorporated in other external circuitry such as light-
ning protection. Except for the different input series resis-
tance, the HI-8684 and HI-8684-10 are identical.
HOLT INTEGRATED CIRCUITS
2
HI-8683, HI-8684
PARITY
ENB
INA
ESD
PROTECTION
CLK
ERROR
ERROR
DETECT
PARITY
DETECT
RXA
HI-8683 ONLY
CLOCK
&
DATA
DETECT
INB
RINA-10
RINA
RINB
10KΩ
25KΩ
10KΩ
25KΩ
ESD
PROTECTION
&
LINE
RECEIVER
RXB
DATA
BIT 32
BIT 32
BIT
COUNT
32-BIT
SHIFT
REG.
32
32-BIT
RECEIVE 32
BUFFER
32-BIT
TO
8-BIT
MUX
8
D0 - D7
RINB-10
TESTA
TESTB
HI-8684 ONLY
GAP
DETECT
BYTE
COUNT
DATA RDY
GAPCLK
RESET
READ
Figure 1. Block Diagram
FUNCTIONAL DESCRIPTION (cont.)
PROTOCOL DETECTION
ARINC clock and data in the HI-8683 are derived from the
two streams of digital data at the INA and INB inputs and the
resulting One/Zero data is shifted into a 32-bit input register
as illustrated in Figure 3.
In the HI-8684, the One/Zero data shifted into the input reg-
ister is created from either the two digital outputs of the built-
in line receiver (Figure 3) or the TESTA and TESTB inputs
(Figure 4).
For ARINC 561 operation, the INA and INB data streams in-
puts must be derived from the ARINC 561 data, clock and
sync with external logic.
GAP DETECTION
The end of a data word is detected by an internal counter
that times out when a data One or Zero is not received for a
period equal to 16 cycles of the GAPCLK signal. The gap
detection time may vary between 16 and 17 cycles of the
GAPCLK signal since the incoming data and GAPCLK are
not usually synchronous inputs. The required frequency of
GAPCLK is a function of the mininum gap time specified for
the type of ARINC data being received. Table 1 indicates
typical frequencies that may be used for the various data
rates normally encountered.
DATABUS
TYPE
429
BIT PERIOD
(
µ
s)
10
MINIMUM GAP
(
µ
s)
45
GAP CLOCK
MHz
0.75
1.0
1.5
0.1
0.1
0.2
GAP DETECTION
TIME (
µ
s)
21.3 - 22.7
16 - 17
10.7 - 11.3
160 - 170
160 - 170
80 - 85
429
575
561
69 - 133
69 - 133
69 - 133
310 - 599
310 - 599
103 - 200
Table 1 - Typical Gap Detection Times
HOLT INTEGRATED CIRCUITS
3
HI-8683, HI-8684
FUNCTIONAL DESCRIPTION (cont.)
ERROR CHECKING
Once a word gap is detected, the data word in the input reg-
ister is transferred to the receive buffer and checked for er-
rors.
When parity detection is enabled (PARITY ENB high), the
received word is checked for odd parity. If there is a parity
error, the 32nd bit of the received data word is set high.
If parity checking is disabled (PARITY ENB low) the 32nd
bit of the data word is always the 32nd ARINC bit received.
The ERROR flag output is set high upon receipt of a word
gap and the number of bits received since the previous
word gap is less than or greater than 32. The ERROR flag
is reset low when the next valid ARINC word is written into
the receive buffer or when RESET is pulsed low.
READING RECEIVE BUFFER
When the data word is transferred to the receive buffer, the
DATA RDY pin goes high. The data word can then be read
in four 8-bit bytes by pulsing the READ input low as indi-
cated in Figure 5. The first read cycle resets DATA RDY
low and increments an internal counter to the next 8-bit
byte. The counter continues to increment on each read cy-
cle until all four bytes are read. The relationship between
each bit of an ARINC word received and each bit of the four
8-bit data bus bytes is specified in Figure 2.
When a new ARINC word is received it always overwrites
the receive buffer. If the first byte of the previous word has
not been read, then previous data is lost and the receive
buffer will contain the new ARINC word. However, if the
DATA RDY pin goes high between the reading of the first
and fourth bytes, the previous read bytes are no longer
valid because the unread bytes have been overwritten by
the new ARINC word. Also, the next read will be of the first
byte of the new ARINC word since the internal byte counter
is always reset to the first byte when new data is trans-
ferred to the receive buffer.
The built-in differential line receiver on the HI-8684 can be
disabled allowing the data and clock detection circuitry to
be driven directly with digital signals. The logical OR func-
tion of the TESTA and TESTB is defined in Truth Table 1.
The two inputs can be used for testing the receiver logic and
for inputting ARINC 429 type data derived from another
source/ protocol. See Figure 4 for typical test input timing.
The device should always be initialized with RESET imme-
diately after entering the test mode to clear a partial word
that may have been received since the last word gap. Oth-
erwise, an ERROR condition may occur and the first 32
bits of data on the test inputs may not be properly re-
ceived.
Also, when entering the test mode, both TESTA and
TESTB should be set high and held in that state for at
least one word gap period (17 gap clocks) after RESET
goes high.
When exiting the test mode, both test inputs should be held
low and the device initialized with RESET.
Read
1st
2nd
3rd
4th
Byte
Byte 1
Byte 2
Byte 3
Byte 4
Data Bus Bits
D0 - D7
D0 - D7
D0 - D7
D0 - D7
ARINC Bits
ARINC 1 - ARINC 8
ARINC 9 - ARINC 16
ARINC 17 - ARINC 24
ARINC 25 - ARINC 32
FIGURE 2. ORDER OF RECEIVED DATA
RESET
A low on the RESET input sets a flip-flop which initializes
the internal logic. When RESET goes high, the internal
logic remains in the initialized state until the first word gap is
detected preventing reception of a partial word.
TEST MODE (HI-8684 only)
TRUTH TABLE 1.
RINA
-1.50 to +1.50V
-3.25V to -6.50V
+3.25V to +6.50V
X
X
X
X = don't care
RINB
-1.50V to +1.50V
+3.25V to +6.50V
-3.25V to -6.50V
X
X
X
TESTA
0
0
0
0
1
1
TESTB
0
0
0
1
0
1
RXA
0
0
1
0
1
0
RXB
0
1
0
1
0
0
HOLT INTEGRATED CIRCUITS
4
HI-8683, HI-8684
TIMING DIAGRAMS
28
ARINC Data Bits
29
30
31
32
Word Gap
4 Bit Periods Min.
1
2
+5V
0V
+5V
INA (HI-8683 only)
INB (HI-8683 only)
VDIFF
RINA - RINB
(HI-8684 only)
DERIVED DATA
DERIVED CLOCK
FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429
0V
+10V
0V
-10V
28
ARINC Data Bits
29
30
31
32
Word Gap
4 Bit Periods Min.
1
2
+5V
0V
+5V
0V
TESTA
TESTB
DERIVED DATA
DERIVED CLOCK
FIGURE 4 - TEST INPUT TIMING FOR ARINC 429
DERIVED DATA
32nd
ARINC Bit
t
DRDY
t
RDYCLR
DATA RDY
t
RDPW
t
RR
READ
t
RD
D0 - D7
VALID
1st 8-bits
2nd 8-bits
3rd 8-bits
4th 8-bits
t
FD
VALID
VALID
VALID
FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING
HOLT INTEGRATED CIRCUITS
5
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