PRELIMINARY
‡
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• 167 MHz Clock, 333 Mb/s/p data rate
• V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
•
t
RAS lockout (
t
RAP =
t
RCD)
• Backwards compatible with DDR200 and DDR266
MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
DDR333 COMPATIBILITY
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and
t
RAS lockout
for improved timing performance. The 256Mb,
DDR333 device will support an (
t
REFI) average peri-
odic refresh interval of 7.8us.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
The Micron 256Mb data sheet provides full specifi-
cations and functionality unless specified herein.
CONFIGURATION
Architecture
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
64 Meg x 4
32 Meg x 8
16 Meg x 16
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
2K (A0–A9, A11)
8K
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0– A8)
OPTIONS
PART NUMBER
64M4
32M8
16M16
TG
FJ
-6
-6T
-75Z
none
• Configuration
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Package
66-Pin TSOP (OCPL)
60-Ball FBGA (16x9mm)
• Timing - Cycle Time
6ns @ CL = 2.5 (DDR333B–FBGA)
1
6ns @ CL = 2.5 (DDR333B–TSOP)
1
7.5ns @ CL = 2 (DDR266A)
2
• Self Refresh
Standard
KEY TIMING PARAMETERS
3
SPEED
GRADE
-6
-6T
-75Z
NOTE:
CLOCK RATE
CL = 2
1
DATA-OUT ACCESS DQS-DQ
1
CL = 2.5
WINDOW
2
WINDOW
2.15ns
2.0ns
2.5ns
±0.70ns
±0.75ns
±0.75ns
SKEW
+0.35ns
+0.45ns
+0.50ns
133 MHz
133 MHz
133 MHz
167 MHz
167 MHz
133 MHz
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. -75, -8 are also available; see base data sheet.
NOTE:
1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
FBGA 60-BALL PACKAGE DIMENSION
0.850 ±0.075
FBGA PACKAGE PINOUT
x4 (Top View)
SEATING PLANE
C
1
A
B
6.40
1.80
CTR
0.80 TYP
PIN A1 ID
BALL A1
1.20 MAX
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
7
8
9
0.10 C
C
D
E
F
G
H
8.00 ±0.05
61X
∅0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.40
BALL A9
J
K
L
11.00
C
L
1.00
TYP
16.00 ±0.10
M
V
SS
Q
NC
V
SS
NC
V
DD
Q
DQ3
NC
V
SS
Q
NC
NC
V
DD
Q
DQ2
NC
V
SS
Q
DQS
V
SS
V
REF
DM
CK
CK#
A12
CKE
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
NC
DQ1
NC
NC
WE#
RAS#
BA1
A0
A2
V
DD
NC V
DD
Q
V
SS
Q
NC
V
DD
Q
NC
V
SS
Q
NC
V
DD
Q
NC
V
DD
A13
CAS#
CS#
BA0
A10
A1
A3
5.50 ±0.05
x8 (Top View)
Bottom View
1
A
B
C
SUBSTRATE: PLASTIC LAMINATE
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
7
8
9
C
L
3.20 ±0.05
4.50 ±0.05
9 .00 ±0.10
D
E
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .33mm
MOLD COMPOUND: EPOXY NOVOLAC
F
G
H
FBGA PACKAGE MARKING
Due to the physical size of the FBGA package, the full
ordering part number is not printed on the package.
Instead the following package code is utilized.
Top mark contains five fields
• Field 1 (Product Family)
DRAM
DRAM - ES
• Field 2 (Product Type)
2.5 Volt, DDR SDRAM, 60-ball
• Field 3 (Width)
x4 devices
x8 devices
x16 devices
• Field 4 (Density / Size)
256Mb
• Filed 5 (Speed Grade)
-6
-75Z
-75
-8
12345
J
K
L
M
V
SS
Q
DQ7
NC
V
DD
Q
NC
V
SS
Q
NC
V
DD
Q
NC
V
SS
Q
V
SS
V
REF
CK
A12
A11
A8
A6
A4
V
SS
DQ6
DQ5
DQ4
DQS
DM
CK#
CKE
A9
A7
A5
V
SS
V
DD
DQ1
DQ2
DQ3
NC
NC
WE#
RAS#
BA1
A0
A2
V
DD
DQ0
V
DD
Q
V
SS
Q
NC
V
DD
Q
NC
V
SS
Q
NC
V
DD
Q
NC
V
DD
A13
CAS#
CS#
BA0
A10
A1
A3
x16 (Top View)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
7
8
9
A
B
C
D
D
Z
L
B
C
D
H
J
P
F
C
E
F
G
H
J
K
L
M
V
SS
Q
DQ14
DQ12
DQ10
DQ8
V
REF
DQ15
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
CK
A12
A11
A8
A6
A4
V
SS
DQ13
DQ11
DQ9
UDQS
UDM
CK#
CKE
A9
A7
A5
V
SS
V
DD
DQ2
DQ4
DQ6
LDQS
LDM
WE#
RAS#
BA1
A0
A2
V
DD
DQ0
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
DD
CAS#
CS#
BA0
A10
A1
A3
V
DD
Q
DQ1
DQ3
DQ5
DQ7
A13
Example top mark for a MT46V32M4FJ-6: DLBFJ
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
66-PIN TSOP PACKAGE DIMENSION
66-PIN TSOP PACKAGE PIN ASSIGMENT
22.22 ± 0.08
0.71
0.65 TYP
0.32 ± .075 TYP
0.10 (2X)
SEE DETAIL A
(TOP VIEW)
x4
x8
x16
V
DD
V
DD
V
DD
NC
DQ0
DQ0
V
DD
Q V
DD
Q
V
DD
Q
NC
DQ1
NC
DQ0
DQ1
DQ2
V
SS
Q
V
SS
Q
VssQ
NC
DQ3
NC
NC
DQ2
DQ4
V
DD
Q V
DD
Q
V
DD
Q
NC
NC
DQ5
DQ1
DQ3
DQ6
V
SS
Q
V
SS
Q
VssQ
NC
DQ7
NC
NC
NC
NC
V
DD
Q V
DD
Q
V
DD
Q
NC
NC
LDQS
NC
NC
NC
V
DD
V
DD
V
DD
DNU
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS#
CAS#
RAS#
RAS#
RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
V
DD
V
DD
V
DD
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x4
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
11.76 ±0.10
10.16 ±0.08
PIN #1 ID
+0.03
0.15 -0.02
0.10
1.20 MAX
GAGE PLANE
0.25
0.10
+0.10
-0.05
0.80 TYP
0.50 ±0.10
DETAIL A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
NOTE:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PIN DESCRIPTIONS
BALL / PIN NUMBERS
FBGA
TSOP
G2, G3
45, 46
SYMBOL
CK, CK#
TYPE
Input
DESCRIPTION
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after V
DD
is applied.
Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. For the x16 , LDM is
DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC
on x4 and x8
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.
H3
44
CKE
Input
H8
24
CS#
Input
H7, G8, G7
3F
F7, 3F
23, 22, 21
47
20, 47
RAS#, CAS#,
WE#
DM
LDM, UDM
Input
Input
J8,J7
K7, L8, L7
M8, M2, L3
L2, K3, K2
J3, K8, J2
H2
26, 27
29-32
32, 35, 36
36, 38, 39
40, 29, 41
42
BA0, BA1
Input
A0, A1, A2
Input
A3, A4, A5
A6, A7, A8
A9, A10, A11
A12
(continued on next page)
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PIN DESCRIPTIONS (continued)
BALL / PIN NUMBERS
FBGA
TSOP
A8, B9, B7
C9, C7, D9
D7, E9, E1
D3, D1, C3
C1, B3, B1,
A2
A8, B7, C7,
D7, D3, C3,
B3, A2
B7, D7, D3,
B3
E3
E7, E3
2, 4, 5,
7, 8, 10
11, 13, 54
56, 57, 59
60, 62, 63,
65
2, 5, 8,
11, 56, 59
62, 65
5, 11, 56
62
51
16, 51
SYMBOL
DQ0-2
DQ3-5
DQ6-8
DQ9-11
DQ12-14
DQ15
DQ0-2
DQ3-5
DQ6-7
DQ0-2
DQ2
DQS
LDQS, UDQS
TYPE
I/O
DESCRIPTION
Data Input/Output: Data bus for
x16
I/O
Data Input/Output: Data bus for
x8
I/O
I/O
Data Input/Output: Data bus for
x4
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS
IS DQS for DQ8-DQ15. Pin 16 (H7) is NC on x4 and x8.
No Connect: These pins should be left unconnected.
Do Not Use: Must float to minimize noise on Vref
DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved
noise immunity.
DQ Ground. Isolated on the die for improved noise immunity.
Power Supply: +2.5V ±0.2V.
Ground.
SSTL_2 reference voltage.
Address input A13 for 1Gb devices.
14, 17, 25,
43, 53
19, 50
B2, D2, C8, 3, 9, 15, 55,
E8, A9
61
A1, C2, E2, 6, 12, 52,
B8, D8
58, 64
F8, M7, A7
A1, A3, F2,
M3
F1
F9
49
17
1, 18, 33
34, 48, 66
NC
DNU
V
DD
Q
V
SS
Q
V
DD
V
SS
V
REF
A13
-
–
Supply
Supply
Supply
Supply
Supply
I
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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