INTEGRATED CIRCUITS
DATA SHEET
SAA5250
Interface for data acquisition and
control
(for multi-standard teletext
systems)
Product specification
File under Integrated Circuits, IC02
January 1987
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
GENERAL DESCRIPTION
SAA5250
The SAA5250 is a CMOS Interface for Data Acquisition and Control (CIDAC) designed for use in conjunction with the
Video Input Processor (SAA5230) in a multi-standard teletext decoder. The device retrieves data from a user selected
channel (channel demultiplexer), as well as providing control signals and consecutive addressing space necessary to
drive a 2 K bytes buffer memory.
The system operates in accordance with the following transmission standards:
•
French Didon Antiope specification D2 A4-2 (DIDON)
•
North American Broadcast Teletext specification (NABTS)
•
U.K. teletext (CEEFAX)
Features
•
7,5 MHz maximum conversion rate
•
Three prefixes; DIDON, NABTS and U.K. teletext (CEEFAX)
•
Mode without prefix
•
Internal calculation of the validation (VAL) and colour burst blanking (CBB) signals, if programmed
•
Programmable framing code and channel numbers
•
Error parity calculation or not (odd parity)
•
Hamming processing of the prefix byte
•
Full channel or VBI reception
•
Slow/fast mode (detection of page flags or not)
•
Maximum/default format up to 63 bytes
•
Addressing space of 2 K bytes of the static memory
•
Multiplexed address/data information is compatible with Motorola or Intel microcontrollers
•
CIDAC is ‘MOTEL’ compatible
PACKAGE OUTLINES
SAA5250P: 40-lead DIL; plastic (SOT129); SOT129-1; 1996 December 02.
SAA5250T: 40-lead mini-pack; plastic (VSO40); SOT158-1; 1996 December 02.
January 1987
2
k, full pagewidth
January 1987
PAGE DETECTION
9-16
SEQUENCE
CONTROLLER
CHANNEL
COMPARATOR
17
HAMMING
CORRECTOR
18
INTERFACE
21
19
ALE
CS
RD
WR
PROGRAM
REGISTER
8
DB7
to
DB0
REGISTER
Philips Semiconductors
FRAMING
CODE
DETECTION
SD
6
SERIAL
REGISTER
PARALLEL
REGISTER
SERIAL/PARALLEL
CONVERTER
Interface for data acquisition and control
(for multi-standard teletext systems)
DCK
FORMAT
TRANSCODER
2 K BYTE
FIFO MEMORY
CONTROLLER
5
3
SAA5250
FORMAT
COUNTER
MEMORY INTERFACE
11
7
8
1, 39-30
8
29-22
40
20
MS
WE
A10 to A0
D7 to D0
V
DD
V
SS
CLOCK
GENERATION
FORMAT
PROCESSOR
VAL IN/
SYNC
3
VAL OUT
2
CBB
4
VALIDATION
SIGNAL
PROCESSING
MGH075
Product specification
SAA5250
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
handbook, halfpage
A10
VAL OUT
1
2
40 V
DD
39 A9
38 A8
37 A7
36 A6
35 A5
34 A4
33 A3
32 A2
31 A1
VAL IN/
3
SYNC
CBB
DCK
SD
MS
WE
DB7
4
5
6
7
8
9
DB6 10
DB5 11
DB4 12
DB3 13
DB2 14
DB1 15
DB0 16
ALE 17
CS 18
WR 19
VSS 20
MGH074
SAA5250
30 A0
29 D7
28 D6
27 D5
26 D4
25 D3
24 D2
23 D1
22 D0
21 RD
Fig.2 Pinning diagram.
January 1987
4
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
PINNING FUNCTION
MNEMONIC
A10 and
A0 to A9
VAL OUT
VAL IN/SYNC
CBB
DCK
SD
MS
WE
DB7 to DB0
ALE
CE
WR
V
SS
RD
D0 to D7
V
DD
PIN NO.
1 and
30 to 39
2
3
4
5
6
7
8
9 to 16
17
18
19
20
21
22 to 29
40
FUNCTION
SAA5250
Memory address outputs used by CIDAC to address a 2 K byte buffer memory
Validation output signal used to control the location of the window for the framing code.
Validation input signal (line signal) used to give or calculate a window for the framing
code detection
Colour burst blanking output signal used by the SAA5230 as a data slicer reset pulse
Data clock input, in synchronization with the serial data signal
Serial data input, arriving from the demodulator
Chip enable output signal for buffer memory selection
Write command output for the buffer memory
8-bit three state input/output data/address bus used to transfer commands, data and
status between the CIDAC registers and the CPU
Demultiplexing input signal for the CPU data bus
Chip enable input for the SAA5250
Write command input (when LOW)
ground
Read command input (when LOW)
8-bit three state input/output data bus used to transfer data between CIDAC and the
buffer memory
+5
V power supply
January 1987
5
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