Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373 Octal transparent latch (3-State)
74ALS374 Octal D flip-flop (3-State)
FEATURES
74ALS373/74ALS374
•
8-bit transparent latch – 74ALS373
•
8-bit positive edge triggered register – 74ALS374
•
3-State output buffers
•
Common 3-State output register
•
Independent register and 3-State buffer operation
TYPE
74ALS373
TYPICAL
PROPAGATION DELAY
6.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
14mA
TYPICAL
SUPPLY CURRENT
(TOTAL)
17mA
DESCRIPTION
The 74ALS373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in High impedance “off” state,
which means they will neither drive nor load the bus.
The 74ALS374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in High impedance “off” state, which means they will neither
drive nor load the bus.
TYPE
74ALS374
TYPICAL
f
MAX
50MHz
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS373N, 74ALS374N
74ALS373D, 74ALS374D
74ALS373DB, 74ALS374DB
DRAWING
NUMBER
20-pin plastic DIP
20-pin plastic SOL
20-pin plastic SSOP
Type II
SOT146-1
SOT163-1
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D7
E (74ALS373)
OE
CP (74ALS374)
Q0 – Q7
Data inputs
Enable input (active-High)
Output enable inputs (active-Low)
Clock pulse input (active rising edge)
3-State outputs
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
130/240
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
2.6mA/24mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08
2
853–1243 01670
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
LOGIC DIAGRAM – 74ALS374
D0
3
D
CP Q
CP
11
D1
4
D
CP Q
D2
7
D
CP Q
D3
8
D
CP Q
D4
13
D
CP Q
D5
14
D
CP Q
D6
17
D
CP Q
D7
18
D
CP Q
OE
V
CC
= Pin 20
GND = Pin 10
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SF00257
FUNCTION TABLE – 74ALS374
INPUTS
INTERNAL REGISTER
OE
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
CP
↑
↑
↑
↑
↑
Dn
l
h
X
X
Dn
L
H
NC
NC
Dn
Q0 – Q7
L
Load and read register
H
NC
Z
Z
Disable outputs
Hold
OUTPUTS
OPERATING MODE
High-voltage level
High state must be present one setup time before the Low-to-High clock transition
Low-voltage level
Low state must be present one setup time before the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
Not Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
1991 Feb 08
5
DSP 与 ARM 处理器
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