HD74AC175
Quad D-Type Flip-Flop
REJ03D0257–0200Z
(Previous ADE-205-377 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both
true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of
the Clock or D inputs, when Low.
Features
•
Edge-Triggered D-Type Inputs
•
Buffered Positive Edge-Triggered Clock
•
Asynchronous Common Reset
•
True and Complement Output
•
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
Package Type
Package Code Package Abbreviation Taping Abbreviation (Quantity)
FP-16DAV
TTP-16DAV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL(2,000 pcs/reel)
HD74AC175AFPEL SOP-16 pin (JEITA)
HD74AC175TELL
TSSOP-16 pin
HD74AC175ARPEL SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
MR
1
Q
0
2
Q
0
3
D
0
4
D
1
5
Q
1
6
Q
1
7
GND 8
(Top view)
16 V
CC
15 Q
3
14
Q
3
13 D
3
12 D
2
11
Q
2
10 Q
2
9 CP
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC175
Logic Symbol
D
0
CP
D
1
D
2
D
3
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Pin Names
D
0
to D
3
CP
MR
Q
0
to Q
3
Q
0
to
Q
3
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and
Q
outputs. The Clock
and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the Low-to-High
clock (CP) transition, causing individual Q and
Q
outputs to follow. A Low input on the Master Reset (MR) will force
all Q outputs Low and
Q
outputs High independent of Clock or Data inputs. The HD74AC175 is useful for general
logic applications where a common Master Reset and Clock are acceptable.
Truth Table
Inputs
@ t
n
,
MR
= H
Dn
L
H
H :
L :
t
n
:
t
n + 1
High Voltage Level
Low Voltage Level
Bit Time before Clock Pulse
: Bit Time after Clock Pulse
Qn
L
H
Outputs
@ t
n+1
Qn
H
L
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC175
Logic Diagram
MR
CP D
3
D
2
D
1
D
0
D
Q
D
Q
D
Q
D
Q
CP Q
CD
CP Q
CD
CP Q
CD
CP Q
CD
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or ground current per output pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
Tstg
Ratings
–0.5 to 7
–20
20
–0.5 to Vcc+0.5
–50
50
–0.5 to Vcc+0.5
±50
±50
–65 to +150
Unit
V
mA
mA
V
mA
mA
V
mA
mA
°C
V
I
= –0.5V
V
I
= Vcc+0.5V
V
O
= –0.5V
V
O
= Vcc+0.5V
Condition
Recommended Operating Conditions
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
30% to 70% V
CC
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
2 to 6
0 to V
CC
–40 to +85
8
Ratings
V
V
°C
ns/V
V
CC
= 3.0V
V
CC
= 4.5 V
V
CC
= 5.5 V
Unit
Condition
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC175
DC Characteristics
Item
Sym-
bol
V
IH
Vcc
(V)
3.0
4.5
5.5
V
IL
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
V
OL
5.5
3.0
4.5
5.5
3.0
4.5
Input leakage
current
Dynamic output
current*
Quiescent supply
current
I
IN
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.58
3.94
4.94
—
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
0.002
0.001
0.001
—
—
—
—
—
—
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.32
0.32
0.32
±0.1
—
—
8.0
Ta = –40 to
+85°C
°
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.48
3.80
4.80
—
—
—
—
—
—
—
86
–75
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
—
—
80
µA
mA
mA
µA
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Unit
Condition
Input Voltage
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Output voltage
V
OH
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
or V
IH
I
OH
= –12 mA
I
OH
= –24 mA
I
OH
= –24 mA
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
IN
= V
CC
or GND
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
*Maximum
test duration 2.0 ms, one output loaded at a time.
AC Characteristics
Ta = +25°C
C
L
= 50 pF
Min
Typ
Max
149
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
9.5
7.0
8.5
6.0
7.5
5.5
8.5
6.0
—
—
12.0
9.0
13.0
9.5
12.5
9.0
11.0
8.5
Ta = –40°C to +85°C
C
L
= 50 pF
Min
Max
139
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
13.5
9.5
14.5
10.5
13.5
10.0
12.5
9.0
MHz
ns
ns
ns
ns
Item
Maximum clock
frequency
Propagation delay
CP to Q
n
or
Q
n
Propagation delay
CP to Q
n
or
Q
n
Propagation delay
MR
to
Q
n
Propagation delay
MR
to Q
n
Note:
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Unit
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC175
AC Operating Requirements
Ta = +25°C
C
L
= 50 pF
Item
Set-up time, HIGH or LOW
D
n
to CP
Hold time, HIGH or LOW
D
n
to CP
CP pulse width HIGH or LOW
MR
pulse width, LOW
Recovery time
MR
to CP
Note:
Symbol V
CC
(V)*
1
Typ
t
su
3.3
2.0
t
h
t
w
t
w
t
rec
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
1.0
0
0
2.5
2.0
2.5
2.0
–2.0
–1.0
Ta = –40°C
to +85°C
C
L
= 50 pF
Unit
ns
ns
ns
ns
ns
Guaranteed Minimum
4.5
4.5
3.0
1.0
1.0
4.5
3.5
4.5
3.5
0.0
0.0
3.0
1.0
1.0
4.5
3.5
5.0
3.5
0.0
0.0
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
4.5
45.0
Typ
pF
pF
Unit
V
CC
= 5.5 V
V
CC
= 5.0 V
Condition
Rev.2.00, Jul.16.2004, page 5 of 7
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