D
D
D
R
A
FT
D
R
A
FT
D
R
A
FT
R
R
A
FT
A
FT
LPC3141/3143
Rev. 0.16 — 27 May 2010
D
Low-cost, low-power ARM926EJ microcontrollers with USB
High-speed OTG, SD/MMC, and NAND flash controller
D
R
R
A
A
FT
FT
D
D
R
A
FT
D
R
D
R
A
FT
D
R
A
FT
D
FT
D
R
A
A
FT
D
Preliminary data sheet
FT
D
R
R
A
R
A
FT
D
R
A
FT
D
R
A
F
A
FT
D
R
D
R
1. General description
The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four
channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted
at consumer, industrial, medical, and communication markets. To optimize system power
consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock
Generation Unit (CGU) that provides dynamic clock gating and scaling.
A
FT
D
R
A
2. Features and benefits
2.1 Key features
CPU platform
270 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
Internal memory
192 kB embedded SRAM
External memory interface
NAND flash controller with 8-bit ECC and AES decryption support (LPC3143 only)
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
Security
AES decryption engine (LPC3143 only)
Secure one-time programmable memory for AES key storage and customer use
128 bit unique ID per device for DRM schemes
Communication and connectivity
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I
2
S interfaces
Integrated master/slave SPI
Two master/slave I
2
C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Four-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface
System functions
Dynamic clock gating and scaling
Multiple power domains
D
D
D
R
A
FT
NXP Semiconductors
LPC3141/3143
FT
FT
FT
D
D
D
R
R
R
A
A
FT
D
R
A
FT
D
R
A
A
FT
FT
D
D
R
R
A
FT
D
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB
On the LPC3143 only: secure booting using an AES decryption engine from SPI
flash, NAND flash, SD/MMC cards, UART, or USB.
DMA controller
Four 32-bit timers
Watchdog timer
PWM module
Master/slave PCM interface
Random Number Generator (RNG)
General Purpose I/O pins (GPIO)
Flexible and versatile interrupt structure
JTAG interface with boundary scan and ARM debug access
Operating voltage and temperature
Core voltage: 1.2 V
I/O voltages: 1.8 V, 3.3 V
Temperature:
−40 °C
to +85
°C
TFBGA180 package: 12
x
12 mm, 0.8 mm pitch
R
FT
D
R
A
D
R
A
D
R
A
R
R
A
D
R
A
A
FT
D
FT
D
R
A
A
FT
A
FT
D
R
D
R
A
F
R
A
FT
D
FT
D
R
A
FT
3. Ordering information
Table 1.
Ordering information
Package
Name
Description
Version
Type number
LPC3141FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12
×
12
×
0.8 mm SOT570-3
LPC3143FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12
×
12
×
0.8 mm SOT570-3
3.1 Ordering options
Table 2.
Ordering options for LPC3141/3143
Core/bus Total
frequency SRAM
Security High-speed USB
engine
AES
no
yes
Device/
Host/OTG
Device/
Host/OTG
10-bit
I
2
S/
ADC
I
2
C
channels
4
4
MCI
Temperature
SDHC/ range
SDIO/
CE-ATA
−40 °C
to +85
°C
−40 °C
to +85
°C
Type number
LPC3141FET180
LPC3143FET180
270/
90 MHz
270/
90 MHz
192 kB
192 kB
2 each yes
2 each yes
LPC3141_3143
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 0.16 — 27 May 2010
2 of 74
D
D
D
R
A
FT
NXP Semiconductors
LPC3141/3143
FT
FT
FT
D
D
D
R
R
R
A
A
FT
D
R
A
FT
A
FT
FT
D
D
R
R
A
FT
D
D
D
R
A
D
R
A
R
R
A
D
R
A
A
FT
A
FT
D
R
FT
4. Block diagram
JTAG
interface
D
R
R
A
FT
D
R
R
A
F
D
R
A
FT
A
FT
A
FT
D
R
A
D
FT
D
LPC3141/3143
DATA
CACHE 16 kB
R
TEST/DEBUG
INTERFACE
INSTRUCTION
CACHE 16 kB
A
ARM926EJ-S
DMA
CONTROLLER
USB 2.0
HIGH-SPEED
OTG
master
slave
slave
ROM
slave
96 kB ISRAM0
slave
96 kB ISRAM1
slave NAND CONTROLLER AES
(1)
BUFFER
master
slave
INTERRUPT
CONTROLLLER
slave
MPMC
master
master
slave
MULTI-LAYER AHB MATRIX
slave
MCI
SD/SDIO
slave
AHB TO
APB
BRIDGE 0/
ASYNC
slave
AHB TO
APB
BRIDGE 1/
ASYNC
slave
AHB TO
APB
BRIDGE 2/
ASYNC
slave
AHB TO
APB
BRIDGE 3/
ASYNC
slave
AHB TO
APB
BRIDGE 4/
SYNC
APB slave group 0
WDT
SYSTEM CONTROL
CGU
IOCONFIG
APB slave group 4
NAND REGISTERS
DMA REGISTERS
APB slave group 3
I
2
S0
I
2
S1
10-bit ADC
EVENT ROUTER
RNG
OTP
APB slave group 1
TIMER 0/1/2/3
PWM
I
2
C0
(1)
LPC3143 only
APB slave group 2
UART
LCD
SPI
PCM
I
2
C1
002aae081
Fig 1.
LPC3141/3143 block diagram
LPC3141_3143
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 0.16 — 27 May 2010
3 of 74
D
D
D
R
A
FT
NXP Semiconductors
LPC3141/3143
FT
FT
FT
D
D
D
R
R
R
A
A
FT
D
R
A
FT
A
FT
FT
D
D
R
R
A
FT
D
D
D
R
A
D
R
A
R
R
A
D
R
A
A
FT
A
FT
D
R
FT
5. Pinning information
5.1 Pinning
ball A1
index area
D
R
R
A
FT
D
R
R
A
F
D
R
A
FT
A
FT
A
FT
D
R
A
D
FT
LPC3141/3143
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D
R
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
002aae082
Transparent top view
Fig 2.
Table 3.
Row A
1
5
9
13
1
5
9
13
1
5
9
13
1
5
9
13
LPC3141/3143 pinning TFBGA180 package
Pin allocation table
Pin Symbol
2
6
10
14
2
6
10
14
2
6
10
14
2
6
10
14
EBI_A_1_CLE
mGPIO6
FFAST_IN
ADC10B_GPA1
VDDE_IOA
mGPIO5
FFAST_OUT
ADC10B_GPA0
EBI_D_11
VDDI
I2C_SDA0
ADC10B_GPA3
EBI_D_6
VSSE_IOC
I2C_SCL0
BUF_TMS
Pin Symbol
3
7
11
-
3
7
11
-
3
7
11
-
3
7
11
-
EBI_D_9
SPI_CS_OUT0
VSSI
-
EBI_A_0_ALE
SPI_MOSI
GPIO3
-
VSSE_IOA
VSSI
GPIO4
-
EBI_D_13
VDDE_IOC
VDDA12
-
Pin Symbol
4
8
12
-
4
8
12
-
4
8
12
-
4
8
12
-
mGPIO10
SPI_SCK
ADC10B_GNDA
-
mNAND_RYBN2
SPI_CS_IN
VSSE_IOC
-
VSSE_IOA
SPI_MISO
VDDI
-
mNAND_RYBN3
VSSE_IOC
VSSI
-
Pin Symbol
EBI_D_10
mGPIO7
VPP
ADC10B_VDDA33
EBI_D_8
mGPIO8
PWM_DATA
ADC10B_GPA2
EBI_D_7
mGPIO9
VPP
VDDE_IOC
EBI_D_5
VDDE_IOC
VSSE_IOC
BUF_TCK
Row B
Row C
Row D
LPC3141_3143
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 0.16 — 27 May 2010
4 of 74
D
D
D
R
A
FT
NXP Semiconductors
LPC3141/3143
FT
FT
FT
D
D
D
R
R
R
A
A
FT
D
R
A
FT
A
FT
FT
D
D
R
R
A
FT
D
D
D
R
A
D
R
A
R
R
A
D
R
A
A
FT
A
FT
D
R
FT
Table 3.
Row E
1
5
9
13
1
5
13
1
5
13
1
5
13
1
5
13
1
5
9
13
1
5
9
13
1
5
9
13
1
5
9
13
Pin allocation table
…continued
Pin Symbol
2
6
10
14
2
10
14
2
10
14
2
10
14
2
10
14
2
6
10
14
2
6
10
14
2
6
10
14
2
6
10
14
EBI_D_4
mNAND_RYBN0
VDDA12
I2STX_BCK1
EBI_D_1
SCAN_TDO
I2SRX_BCK1
EBI_D_0
I2STX_WS1
I2SRX_DATA1
EBI_NRAS_BLOUT_1
GPIO12
RSTIN_N
EBI_NWE
GPIO1
GPIO14
NAND_NCS_3
mLCD_DB_6
GPIO0
GPIO18
USB_VBUS
VSSI
VDDE_IOC
GPIO2
USB_VDDA33_DRV
VSSE_IOB
I2SRX_DATA0
TCK
USB_DM
mLCD_DB_2
I2SRX_BCK0
mI2STX_CLK0
Pin Symbol
3
7
11
-
3
11
-
3
11
-
3
11
-
3
11
-
3
7
11
-
3
7
11
-
3
7
11
-
3
7
11
-
EBI_D_14
mNAND_RYBN1
ARM_TDO
-
EBI_D_15
BUF_TRST_N
-
EBI_D_12
VSSE_IOC
-
VDDI
GPIO19
-
NAND_NCS_1
GPIO16
-
VSSE_IOA
mLCD_DB_10
VDDE_IOC
-
USB_VSSA_TERM
VDDI
VSSI
-
VSSE_IOB
VDDE_IOB
mI2STX_WS0
-
mLCD_DB_15
mLCD_DB_4
JTAGSEL
-
Pin Symbol
4
8
12
-
4
12
-
4
12
-
4
12
-
4
12
-
4
8
12
-
4
8
12
-
4
8
12
-
4
8
12
-
D
R
R
A
R
A
A
Pin Symbol
EBI_D_3
VDDE_IOA
VSSA12
I2C_SCL1
EBI_D_2
VDDE_IOA
I2SRX_WS1
EBI_NCAS_BLOUT_0
VDDE_IOA
SYSCLK_O
EBI_DQM_0_NOE
VDDE_IOA
GPIO11
NAND_NCS_0
USB_RREF
GPIO15
NAND_NCS_2
mLCD_DB_12
TDI
GPIO20
USB_VDDA12_PLL
mLCD_DB_9
VSSE_IOC
VSSE_IOC
USB_ID
VDDE_IOB
VDDE_IOB
mI2STX_DATA0
USB_GNDA
mLCD_DB_8
mLCD_RW_WR
mUART_CTS_N
FT
D
R
R
A
FT
A
FT
D
F
FT
VSSE_IOA
VDDE_IOC
I2C_SDA1
-
VSSE_IOA
I2STX_DATA1
-
VSSI
VDDE_IOC
-
VSSE_IOA
CLK_256FS_O
-
CLOCK_OUT
GPIO13
-
USB_VSSA_REF
mLCD_CSB
GPIO17
-
VDDE_IOB
mLCD_E_RD
VDDI
-
VSSE_IOB
VSSE_IOB
mI2STX_BCK0
-
mLCD_DB_11
mLCD_DB_0
UART_TXD
-
D
D
R
A
FT
D
R
A
Row F
Row G
Row H
Row J
Row K
Row L
Row M
Row N
LPC3141_3143
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 0.16 — 27 May 2010
5 of 74
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
