Si823x
0.5
AND
4 . 0 A
MP
I S O
D R I V E R S
(2.5
AND
5
K
V
RMS
)
Features
Pin Assignments
Two completely isolated drivers
Independent HS and LS inputs or
in one package
PWM input versions
Up to 5 kV
RMS
input-to-output
Transient immunity >30 kV/µs
isolation
Overlap protection and
Up to 1500 V
DC
peak driver-to-
programmable dead time
driver differential voltage
Wide operating range
HS/LS and dual driver versions
–40 to +125 °C
Up to 8 MHz switching frequency
RoHS-compliant packages
0.5 A peak output (Si8230/1/2)
SOIC-16 narrow body
SOIC-16 wide body
4.0 A peak output (Si8233/4/5/6)
LGA-14
60 ns propagation delay (max)
SOIC-16 (Wide)
VIA
VIB
VDDI
GNDI
DISABLE
DT
NC
VDDI
1
2
3
4
5
6
7
8
16
15
14
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Si8230
Si8233
13
12
11
10
9
Applications
SOIC-16 (Narrow)
VIA
1
2
3
16
15
14
VDDA
VOA
GNDA
NC
NC
VDDB
VOB
GNDB
Power delivery systems
Motor control systems
Isolated dc-dc power supplies
Lighting control systems
Plasma displays
Solar and industrial inverters
VIB
VDDI
GNDI
DISABLE
4
Si8230
13
5
6
7
8
Si8233
12
11
10
9
Safety Approval
DT
NC
UL 1577 recognized
Up
VDE certification conformity
IEC
VDDI
to 5000 Vrms for 1 minute
CSA component notice 5A
approval
IEC
60747-5-2 (VDE 0884 Part 2)
EN 60950-1 (reinforced insulation)
GNDI
VIA
VIB
VDDI
DISABLE
LGA-14 (5 x 5 mm)
1
2
3
4
5
6
7
14
13
12
60950-1, 61010-1, 60601-1
(reinforced insulation)
VDDA
VOA
GNDA
NC
VDDB
VOB
GNDB
Description
The Si823x isolated driver family combines two independent, isolated
drivers into a single package. The Si8230/1/3/4 are high-side/low-side
drivers, and the Si8232/5/6 are dual drivers. Versions with peak output
currents of 0.5 A (Si8230/1/2) and 4.0 A (Si8233/4/5/6) are available. All
drivers operate with a maximum supply voltage of 24 V.
The Si823x drivers utilize Silicon Labs' proprietary silicon isolation
technology, which provides up to 5 kV
RMS
withstand voltage per UL1577
and fast 60 ns propagation times. Driver outputs can be grounded to the
same or separate grounds or connected to a positive or negative voltage.
The TTL level compatible inputs with >400 mV hysteresis are available in
individual control input (Si8230/2/3/5/6) or PWM input (Si8231/4)
configurations. High integration, low propagation delay, small installed
size, flexibility, and cost-effectiveness make the Si823x family ideal for a
wide range of isolated MOSFET/IGBT gate drive applications.
Si8230
Si8233
11
10
7
8
DT
VDDI
Patents Pending
Rev. 1.0 8/10
Copyright © 2010 by Silicon Laboratories
Si823x
Si823x
T
ABLE
Section
OF
C
ONTENTS
Page
1. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Typical Operating Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Typical Operating Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1. Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.5. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.7. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1. High-Side / Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2. Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3. Dual Driver with Thermally Enhanced Package (Si8236) . . . . . . . . . . . . . . . . . . . . .29
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13. Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14. Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
15. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .46
16. Land Pattern: 14 LD LGA with Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
18. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
19. Top Marking: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Rev. 1.0
3
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