CAT1163
Supervisory Circuits with I
2
C Serial CMOS EEPROM,
Precision Reset Controller and Watchdog Timer (16K)
FEATURES
Watchdog timer input (WDI)
400kHz I
2
C bus compatible
2.7V to 6.0V operation
Low power CMOS technology
16-Byte page write buffer
Built-in inadvertent write protection
—
—
—
—
—
V
CC
lock out
Write protect pin, WP
Precision power supply voltage monitor
5V, 3.3V and 3V systems
Five threshold voltage options
EEPROM memory (16K) with hardware memory write
protection, a system power supervisor with brown out
protection and a watchdog timer are integrated
together in low power CMOS technology. Memory
interface is via an I
2
C bus.
The 1.6-second watchdog circuit returns a system to a
known good state if a software or hardware glitch
halts or “hangs” the system. The CAT1163 watchdog
monitors the WDI input pin.
The power supply monitor and reset circuit protects
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition, a
reset pin can be used as debounced input for push-
button manual reset capability.
The CAT1163 memory features a 16-byte page. In
addition, hardware data protection is provided by a
write protect pin WP and by a V
CC
sense circuit that
prevents writes to memory whenever V
CC
falls below
the reset threshold or until V
CC
reaches the reset
threshold during power up.
Available packages include an 8-pin DIP and a
surface mount, 8-pin SO package.
Active high or low reset
1,000,000 Program/Erase cycles
Manual reset
100 Year data retention
8-pin DIP or 8-pin SOIC
Commercial and industrial temperature ranges
For Ordering Information details, see page 13.
DESCRIPTION
The CAT1163 is a complete memory and supervisory
solution for microcontroller-based systems. A serial
PIN CONFIGURATION
PDIP 8 Lead
SOIC 8 Lead
WDI
¯¯¯¯¯¯
RESET
WP
GND
1
2
3
4
CAT1163
8
7
6
5
V
CC
RESET
SCL
SDA
PIN FUNCTIONS
Pin Name
WDI
¯¯¯¯¯¯
RESET
WP
GND
SDA
SCL
RESET
V
CC
Function
Warchdog Timer Input
Active Low Reset I/O
Write Protect
Ground
Serial Data/Address
Clock Input
Active High Reset I/O
Power Supply
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-3003 Rev. I
CAT1163
BLOCK DIAGRAM
RESET THRESHOLD OPTION
Part Dash
Number
-45
-42
-30
-28
-25
Minimum
Threshold
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current
(3)
REABILITY CHARACTERISTICS
Symbol
N
END(4)
T
DR(4)
V
ZAP(4)
I
LTH(4)(5)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
Ratings
–55 to +125
–65 to +150
–2.0 to V
CC
+ 2.0
–2.0 to + 7.0
1.0
300
100
Units
ºC
ºC
V
V
W
ºC
mA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
Doc. No. MD-3003 Rev. I
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1163
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7V to 6.0V, unless otherwise specified.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (SDA)
Test Conditions
f
SCL
= 100kHz
V
CC
= 3.3V
V
CC
= 5V
V
IN
= GND or V
CC
V
IN
= GND or V
CC
Min
Typ
Max
3
40
50
2
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
µA
µA
µA
µA
V
V
V
-1
V
CC
x 0.7
I
OL
= 3 mA, V
CC
= 3.0V
CAPACITANCE
T
A
= 25ºC, f = 1.0MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
V
CC
= 2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF.
V
CC
= 2.7V - 6V V
CC
= 4.5V – 5.5V
Symbol
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F
(1)
Parameter
Clock Frequency
Noise Suppresion Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission
Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Min
Max
100
200
3.5
Min
Max
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
4.7
4
4.7
4
4.7
0
50
1
300
4
100
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
µs
ns
µs
ns
t
SU:STO
t
DH
POWER-UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specific operation can be initiated.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-3003 Rev. I
CAT1163
WRITE CYCLE LIMITS
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
10
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave address.
RESET CIRCUIT CHARACTERISTICS
Symbol
t
GLITCH
V
RT
V
OLRS
V
OHRS
Parameter
Glitch Reject Pulse Width
Reset Threshold Hystersis
Reset Output Low Voltage (I
OLRS
= 1mA)
Reset Output High Voltage
Reset Threshold (V
CC
= 5V)
(CAT1163-45)
Reset Threshold (V
CC
= 5V)
(CAT1163-42)
V
TH
Reset Threshold (V
CC
= 3.3V)
(CAT1163-30)
Reset Threshold (V
CC
= 3.3V)
(CAT1163-28)
Reset Threshold (V
CC
= 3V)
(CAT1163-25)
t
PURST
t
WP
t
RPD
V
RVALID
Power-Up Reset Timeout
Watchdog Period
V
TH
to RESET Output Delay
RESET Output Valid
1
V
CC
- 0.75
4.50
4.25
3.00
2.85
2.55
130
1.6
5
4.75
4.50
3.15
3.00
2.70
270
ms
sec
µs
V
V
15
0.4
Min
Typ
Max
100
Units
ns
mV
V
V
Doc. No. MD-3003 Rev. I
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1163
PIN DESCRIPTION
WDI: WATCHDOG INPUT
If there is no transition on the WDI for more than 1.6
seconds, the watchdog timer times out.
WP: WRITE PROTECT
If the pin is tied to V
CC
the entire memory array
becomes Write Protected (READ only). When the pin
is tied to GND or left floating normal read/write
operations are allowed to the device.
¯¯¯¯¯¯
RESET/RESET: RESET I/O
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins
the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-
¯¯¯¯¯¯
down resistor, and the RESET pin must be connected
through a pull-up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
SCL: SERIAL CLOCK
Serial clock input.
RESET outputs. During power-up, the RESET outputs
remain active until V
CC
reaches the V
TH
threshold and
will continue driving the outputs for approximately
200ms (t
PURST
) after reaching V
TH
. After the t
PURST
timeout interval, the device will cease to drive the
reset outputs. At this point the reset outputs will be
pulled up or down by their respective pull up/down
resistors. During power-down, the RESET outputs will
¯¯¯¯¯¯
be active when V
CC
falls below V
TH
. The RESET
outputs will be valid so long as V
CC
is >1.0V (V
RVALID
).
The RESET pins are I/Os; therefore, the CAT1163
can act as a signal conditioning circuit for an
externally applied manual reset. The inputs are edge
triggered; that is, the RESET input in the CAT1163 will
initiate a reset timeout after detecting a low to high
¯¯¯¯¯¯
transition and the RESET input in the CAT1163 will
initiate a reset timeout after detecting a high to low
transition.
Watchdog Timer
The Watchdog Timer provides an independent
protection for microcontrollers. During a system
failure, the CAT1163 will respond with a reset signal
after a time-out interval of 1.6 seconds for a lack of
activity. The CAT1163 is designed with the Watchdog
Timer feature on the WDI input. If the microcontroller
does not toggle the WDI input pin within 1.6 seconds,
the Watchdog Timer times out. This will generate a
reset condition on reset outputs. The Watchdog Timer
is cleared by any transition on WDI.
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared.
DEVICE OPERATION
Reset Controller Description
The CAT1163 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
Figure 1. RESET Output Timing
t
GLITCH
V
TH
V
RVALID
V
CC
t
PURST
t
RPD
t
PURST
RESE T
t
RPD
RESE T
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-3003 Rev. I
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