74HC3GU04
Triple unbuffered inverter
Rev. 5 — 2 October 2013
Product data sheet
1. General description
The 74HC3GU04 is a triple unbuffered inverter. Inputs include clamp diodes. This enables
the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Symmetrical output impedance
High noise immunity
Low-power dissipation
Balanced propagation delays
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC3GU04DP
74HC3GU04DC
74HC3GU04GD
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP8
VSSOP8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
Type number
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3
2
0.5 mm
4. Marking
Table 2.
Marking
Marking code
[1]
HU4
HU4
HU4
Type number
74HC3GU04DP
74HC3GU04DC
74HC3GU04GD
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
NXP Semiconductors
74HC3GU04
Triple unbuffered inverter
5. Functional diagram
1
1
7
1
1A
1Y
7
3
1
5
3
2A
2Y
5
1
6
3A
3Y
2
6
2
mna720
mna721
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
6. Pinning information
6.1 Pinning
74HC3GU04
1A
1
2
3
4
8
7
6
5
V
CC
1Y
3A
2Y
74HC3GU04
1A
3Y
2A
GND
1
2
3
4
001aak022
3Y
8
7
6
5
V
CC
1Y
3A
2Y
2A
GND
001aak023
Transparent top view
Fig 3.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 4.
Pin configuration SOT996-2 (XSON8)
6.2 Pin description
Table 3.
Symbol
1A, 2A, 3A
1Y, 2Y, 3Y
GND
V
CC
Pin description
Pin
1, 3, 6
7, 5, 2
4
8
Description
data input
data output
ground (0 V)
supply voltage
74HC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 2 October 2013
2 of 17
NXP Semiconductors
74HC3GU04
Triple unbuffered inverter
7. Functional description
Table 4.
Input
nA
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Output
nY
H
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
quiescent supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
[1]
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
Max
+7.0
20
20
25
50
-
+150
300
Unit
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 package: above 55
C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110
C
the value of P
tot
derates linearly with 8 mW/K.
For XSON8 package: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
t/V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Unit
V
V
V
C
ns/V
ns/V
ns/V
74HC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 2 October 2013
3 of 17
NXP Semiconductors
74HC3GU04
Triple unbuffered inverter
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level input
voltage
Conditions
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level input
voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
[1]
40 C
to +85
C
Min
1.7
3.6
4.8
-
-
-
1.9
4.4
5.9
4.13
5.63
-
-
-
-
-
-
-
-
Typ
[1]
1.1
2.4
3.1
0.9
2.1
2.9
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
-
-
3.0
Max
-
-
-
0.3
0.9
1.2
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
10
-
40 C
to +125
C
Min
1.7
3.6
4.8
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
Max
-
-
-
0.3
0.9
1.2
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
20
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
input leakage current
supply current
input capacitance
V
I
= V
CC
or GND; V
CC
= 6.0 V
per input pin; V
I
= V
CC
or GND;
I
O
= 0 A; V
CC
= 6.0 V
All typical values are measured at T
amb
= 25
C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 6.
Symbol Parameter
t
pd
Conditions
[2]
40 C
to +85
C
Min
Typ
[1]
13
6
5
Max
75
15
13
40 C
to +125
C
Unit
Min
-
-
-
Max
90
18
15
ns
ns
ns
propagation delay nA to nY; see
Figure 5
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
-
-
-
74HC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 2 October 2013
4 of 17
NXP Semiconductors
74HC3GU04
Triple unbuffered inverter
Table 8.
Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 6.
Symbol Parameter
t
t
transition time
Conditions
nY; see
Figure 5
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power dissipation V
I
= GND to V
CC
capacitance
All typical values are measured at T
amb
= 25
C.
t
pd
is the same as t
PLH
and t
PHL
.
t
t
is the same as t
TLH
and t
THL
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC2
f
o
) = sum of outputs.
[4]
[3]
40 C
to +85
C
Min
-
-
-
-
Typ
[1]
18
6
5
5
Max
95
19
16
-
40 C
to +125
C
Unit
Min
-
-
-
-
Max
125
25
20
-
ns
ns
ns
pF
[1]
[2]
[3]
[4]
12. Waveforms
V
I
nA input
GND
t
PHL
V
OH
nY output
V
OL
t
THL
V
M
V
M
10 %
V
M
V
M
t
PLH
90 %
t
TLH
mna722
Measurement points are given in
Table 9.
Fig 5.
Table 9.
Type
Propagation delay data input (nA) to data output (nY) and transition time output (nY)
Measurement points
Input
V
M
0.5
V
CC
Output
V
M
0.5
V
CC
74HC3GU04
74HC3GU04
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 5 — 2 October 2013
5 of 17
嵌入式系统
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