Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
INTEGRATED CIRCUITS
74F51
Dual 2-wide 2-input, 2-wise 3-input
AND-OR-invert gate
Product specification
IC15 Data Handbook
1989 Mar 03
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
74F51
TYPE
74F51
TYPICAL
PROPAGATION
DELAY
3.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
3.5mA
PIN CONFIGURATION
D0a
D1a
D1b
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
D0c
D0b
D0f
D0e
D0d
Q0
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F51N
N74F51D
PKG DWG #
SOT27-1
SOT108-1
D1c
D1d
Q1
GND
SF00085
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
Dna, Dnb, Dnc, Dnd, Dne, Dnf Data inputs
1.0/1.0
Q0, Q1
Data outputs
50/33
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
1.0mA/20mA
LOGIC SYMBOL
IEC/IEEE SYMBOL
9
&
1
1
12
13
9
10
11
2
3
4
5
10
11
8
13
D0a D0b D0c D0d D0e D0f D1a D1b D1c D1d
12
1
Q0
Q1
2
3
8
V
CC
= Pin 14
GND = Pin 7
6
4
5
&
&
&
1
6
SF00086
SF00087
LOGIC DIAGRAM
D0a
D0b
D0c
D0d
D0e
D0f
1
12
13
8
9
10
11
Q0
FUNCTION TABLE FOR 3-INPUT GATES
D0a
H
X
INPUTS
D0b
D0c
D0d
D0e
H
H
X
X
X
X
H
H
All other combinations
D0f
X
H
OUTPUT
Q0
L
L
H
D1a
D1b
D1c
D1d
V
CC
= Pin 14
GND = Pin 7
2
3
6
4
5
Q1
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
FUNCTION TABLE FOR 2-INPUT GATES
INPUTS
D1a
D1b
H
X
D1c
X
H
D1d
X
H
H
X
OUTPUT
Q1
L
L
H
SF00088
All other combinations
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
March 3, 1989
2
853–0054 95962
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
74F51
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
+70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OH
= MAX
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input
voltage
High-level input current
Low-level input current
Short-circuit output current
3
Supply current (total)
I
CCH
I
CCL
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
V
IN
= GND
V
IN
= 4.5V
–60
1.8
5.5
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
LIMITS
MIN
2.5
2.7
3.4
0.30
0.30
–0.73
0.50
0.50
–1.2
100
20
–0.6
–150
3.0
7.5
TYP
2
MAX
UNIT
V
V
V
V
V
µA
µA
mA
mA
mA
mA
V
O
OH
High level output voltage
High-level
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
March 3, 1989
3
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
74F51
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF, R
L
= 500Ω
MIN
t
PLH
t
PHL
Propagation delay
Dna, Dnb, Dnc, Dnd, Dne, Dnf to Qn
Waveform 1
2.0
1.0
TYP
3.5
2.5
MAX
5.5
4.0
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF, R
L
= 500Ω
MIN
1.5
1.0
MAX
6.5
4.5
ns
UNIT
AC WAVEFORMS
Dna, Dnb, Dnc, Dnd, Dne, Dnf
V
M
t
PHL
V
M
t
PLH
Qn
V
M
V
M
SF00089
Waveform 1. Propagation Delay for Inverting Outputs
NOTE:
For all waveforms, V
M
= 1.5V.
TEST CIRCUIT AND WAVEFORM
V
CC
NEGATIVE
PULSE
V
IN
PULSE
GENERATOR
R
T
D.U.T.
V
OUT
90%
V
M
10%
t
THL (
t
f
)
C
L
R
L
t
w
V
M
10%
t
TLH (
t
r
)
0V
90%
AMP (V)
t
TLH (
t
r
)
90%
POSITIVE
PULSE
V
M
10%
t
w
t
THL (
t
f
)
AMP (V)
90%
V
M
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude V
M
74F
3.0V
1.5V
rep. rate
1MHz
t
w
500ns
t
TLH
2.5ns
t
THL
2.5ns
SF00006
March 3, 1989
4
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