电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

UPC1663G

产品描述OP-AMP, PDSO8
产品类别配件   
文件大小44KB,共5页
制造商NEC ( Renesas )
官网地址https://www2.renesas.cn/zh-cn/
下载文档 全文预览

UPC1663G概述

OP-AMP, PDSO8

文档预览

下载PDF文档
ULTRA-WIDEBAND UPC1663G
DIFFERENTIAL VIDEO AMPLIFIER
FEATURES
Single Ended Voltage Gain, A
VS
(dB)
SINGLE ENDED VOLTAGE GAIN
vs. FREQUENCY
• BANDWIDTH AND TYPICAL GAIN
120 MHz at A
VOL
= 300
170 MHz at A
VOL
= 100
700 MHz at A
VOL
= 10
• VERY SMALL PHASE DELAY
• GAIN ADJUSTABLE FROM 10 TO 300
• NO FREQUENCY COMPENSATION REQUIRED
60
50
40
30
20
10
0
Gain 2
Gain 1
DESCRIPTION
The UPC1663G is a video amplifier with differential input and
output stages. A high frequency process (f
T
= 6 GHz) improves
AC performance compared with industry-standard video am-
plifiers. This device is excellent as a sense amplifier for high-
density CCDs, as a video or pulse amplifier in high-resolution
displays, and in communications equipment.
100 k
1M
10 M
100 M
Frequency, f (Hz)
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C, V
CC
=
±6
V, R
S
= 50
Ω,
f = 10 MHz)
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
I
CC
A
Vd
BW
t
R
t
pd
R
IN
C
IN
I
IO
I
B
V
N
V
I
CMRR
SVRR
V
O(off)
PARAMETERS AND CONDITIONS
Power Supply Current
Gain
1
Gain
2
Bandwidth (Gain is 3 dB down
from the gain at 100 KHz)
Rise Time, V
OUT
= 1V
p-p:
Differential Voltage Gain:
Propagation Delay, V
OUT
= 1 Vp-p:
Input Impedance:
Input Capacitance
Input Offset Current
Input Bias Current
Input Noise Voltage, 10 k to 10 MHz
Input Voltage Range
Common Mode Rejection Ratio, Vcm =
±1
V, f
≤100
kHz
Vcm =
±1
V, f = 5 MHz
Supply Voltage Rejection Ratio,
∆V
=
±0.5
V
Output Offset Voltage, V
O(off)
= |OUT1 - OUT2|
Gain
1
Gain
2
Output Common Mode Voltage
Max. Output Voltage Swing, single-ended
Output Sink Current
UNITS
mA
MIN
200
8
Gain
1
Gain
2
Gain
1
Gain
2
Gain
1
Gain
2
Gain
1
Gain
2
MHz
MHz
ns
ns
ns
ns
kΩ
kΩ
pF
µA
µA
µV
r.m.s.
V
dB
dB
dB
V
V
V
Vp-p
mA
±1.0
55
53
50
UPC1663G
G08
TYP
13
320
10
120
700
2.9
2.7
2
1.2
4.0
180
2
0.4
20
3
70
60
70
0.3
0.1
2.9
4.0
3.6
1.5
1.0
3.4
5.0
40
MAX
20
500
12
50
V
O (CM)
V
Op-p
I
sink
2.4
3.0
2.5
Notes:
1. Gain select pins GA and GB are connected together.
2. All gain select pins are open.
3. Insert adjustment resistor (0 to 10 kΩ) between GA and GB when variable gain is necessary.
California Eastern Laboratories

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 248  1389  1151  1965  6  5  28  24  40  1 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved