S i 5 3 4 1 /4 0
L
O W
- J
I T T E R
, 1 0 - O
U T P U T
, A
NY
-F
R E Q U E N C Y
, A
NY
-O
U T P U T
C
LOCK
G
ENERATOR
Features
Generates up to 10 independent
output clocks
Ultra-low jitter: <100 fs RMS typical
MultiSynth™ technology enables any-
frequency synthesis on any-output
Highly configurable outputs
compatible with LVDS, LVPECL, CML,
LVCMOS, HCSL, or programmable
voltage
Input frequency range:
External crystal: 25, 48-54 MHz
Differential clock: 10 to 750 MHz
LVCMOS clock: 10 to 250 MHz
Output frequency range:
Differential: 100 Hz to 712.5 MHz
LVCMOS: 100 Hz to 250 MHz
Output-output skew: 20 ps typ
Adjustable output-output delay
Optional zero delay mode
Independent glitchless on-the-fly
output frequency changes
DCO mode with frequency steps as
low as 0.001 ppb
Independent output clock supply pins:
3.3 V, 2.5 V, or 1.8 V
Built-in power supply filtering and
regulation
Status monitoring: LOS, LOL
Serial Interface: I
2
C or SPI (3-wire or
4-wire)
User programmable (2x) non-volatile
OTP memory
ClockBuilder Pro software utility
simplifies device configuration and
assigns customer part numbers
Si5341:
4 input, 10 output, compact
9x9 mm, 64 QFN
Si5340:
4 input, 4 output, compact
7x7 mm, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
TM
9x9 mm
7x7 mm
Ordering Information
See Section 8.
Functional Block Diagram
Si5341/40
IN_SEL[1:0]
IN0
÷INT
÷INT
÷INT
Device Selector Guide
Grade
Si534xA
Si534xB
Si534xC
Si534xD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Mode
Integer + Fractional
Integer Only
IN1
IN2
XTAL
XA
PLL
OSC
XB
FB_IN
÷INT
Applications
Clock tree generation replacing XOs,
buffers, signal format translators
Any-frequency clock translation
Clocking for FPGAs, processors,
memory
Ethernet switches/routers
OTN framers/mappers/processors
Test equipment & instrumentation
Broadcast video
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
Description
The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL
with proprietary MultiSynth fractional synthesizer technology to offer a versatile and
high performance clock generator platform. This highly flexible architecture is capable
of synthesizing a wide range of integer and non-integer related frequencies up to
712.5 MHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter
performance with 0 ppm error. Each of the clock outputs can be assigned its own
format and output voltage enabling the Si5341/40 to replace multiple clock ICs and
oscillators with a single device making it a true “clock tree on a chip”.
The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software.
Custom part numbers are automatically assigned using a
ClockBuilder Pro
for fast,
free, and easy factory pre-programming, or the Si5341/40 can be programmed in-
circuit via I
2
C and SPI serial interfaces.
Si5340
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
NVM
I
2
C/SPI
Control/
Status
÷INT
÷INT
÷INT
÷INT
Si5341
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si5341/40
Si5341/40
T
ABLE
O
F
C
ON TENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1. Power-up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3. Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.5. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.6. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.7. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.8. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.9. Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.10. Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro
for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
9.1. Si5341 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
9.2. Si5340 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Rev. 1.0
3
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