S i 5 3 0 / 5 31
R
EVISION
D
C
R YS TA L
O
SCILLATOR
(XO) (10 M H
Z T O
1 . 4 GH
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
1
6
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
OE
2
5
CLK–
GND
3
4
CLK+
Si530 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
2
5
NC
GND
3
4
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
1
6
V
DD
NC
2
5
CLK–
GND
3
4
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.2 5/11
Copyright © 2011 by Silicon Laboratories
Si530/531
Si530/531
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
Tristate mode
Output Enable (OE)
2
Min
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
111
99
90
81
60
—
—
—
Max
3.63
2.75
1.89
121
108
98
88
75
—
0.5
85
Units
V
V
V
mA
mA
V
V
ºC
V
IH
V
IL
Operating Temperature Range
T
A
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2.
OE pin includes a 17 k pullup resistor to V
DD
.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2
Symbol
f
O
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
10
—
–7
–20
–50
Typ
—
—
±1.5
—
—
—
—
—
Max
945
160
—
+7
+20
+50
±3
±10
Units
MHz
MHz
ppm
Initial Accuracy
Temperature Stability
1,3
f
i
Measured at +25 °C at time of
shipping
ppm
ppm
ppm
Aging
f
a
Frequency drift over first year
Frequency drift over 20 year
life
—
—
Notes:
1.
See Section 3. "Ordering Information" on page 7 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Selectable parameter specified by part number.
4.
Time from powerup or tristate mode to f
O
.
2
Rev. 1.2
Si530/531
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Total Stability
Symbol
Test Condition
Temp stability = ±7 ppm
Temp stability = ±20 ppm
Temp stability = ±50 ppm
Min
—
—
—
—
Typ
—
—
—
—
Max
±20
±31.5
±61.5
10
Units
ppm
ppm
ppm
ms
Powerup Time
4
t
OSC
Notes:
1.
See Section 3. "Ordering Information" on page 7 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Selectable parameter specified by part number.
4.
Time from powerup or tristate mode to f
O
.
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
—
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.7
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
V
O
2.5/3.3 V option mid-level
1.8 V option mid-level
2.5/3.3 V option swing (diff)
V
OD
—
—
1.10
0.35
0.8 x V
DD
V
DD
– 1.30
V
DD
– 0.36
1.50
0.425
—
—
—
1
—
—
1.90
0.50
V
DD
V
V
V
PP
V
PP
V
V
1.8 V option swing (diff)
I
OH
= 32 mA
I
OL
= 32 mA
CMOS Output Option
3
V
OH
V
OL
—
—
—
0.4
350
—
Rise/Fall time (20/80%)
t
R,
t
F
LVPECL/LVDS/CML
CMOS with C
L
= 15 pF
ps
ns
Symmetry (duty cycle)
SYM
LVPECL:
(diff)
LVDS:
CMOS:
V
DD
– 1.3 V
1.25 V (diff)
V
DD
/2
45
—
55
%
Notes:
1.
50
to V
DD
– 2.0 V.
2.
R
term
= 100
(differential).
3.
C
L
= 15 pF
Rev. 1.2
3
Si530/531
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1
for F
OUT
> 500 MHz
Phase Jitter (RMS)
1
for F
OUT
of 125 to 500 MHz
Phase Jitter (RMS)
for F
OUT
of 10 to 160 MHz
CMOS Output Only
Symbol
Test Condition
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Min
—
—
—
—
—
—
Typ
0.25
0.26
0.36
0.34
0.62
0.61
Max
0.40
0.37
0.50
0.42
—
—
Units
ps
ps
ps
ps
ps
ps
J
J
J
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
2
12 kHz to 20 MHz (OC-48)
2
50 kHz to 20 MHz
2
Notes:
1.
Refer to AN256 for further information.
2.
Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
2
14
Max
—
—
Units
ps
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Offset Frequency (f)
120.00 MHz
LVDS
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
–112
–122
–132
–137
–144
–150
n/a
156.25 MHz
LVPECL
–105
–122
–128
–135
–144
–147
n/a
622.08 MHz
LVPECL
–97
–107
–116
–121
–134
–146
–148
Units
dBc/Hz
4
Rev. 1.2
Si530/531
Table 7. Environmental Compliance
The Si530/531 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level
Contact Pads
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
J-STD-020, MSL1
Gold over Nickel
Table 8. Absolute Maximum Ratings
1
Parameter
Maximum Operating Temperature
Supply Voltage, 1.8 V Option
Supply Voltage, 2.5/3.3 V Option
Input Voltage (any input pin)
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
Symbol
T
AMAX
V
DD
V
DD
V
I
T
S
ESD
T
PEAK
t
P
Rating
85
–0.5 to +1.9
–0.5 to +3.8
–0.5 to V
DD
+ 0.3
–55 to +125
2500
260
20–40
Units
ºC
V
V
V
ºC
V
ºC
seconds
Notes:
1.
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2.
The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO
for further information, including soldering profiles.
Rev. 1.2
5
FPGA/CPLD
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