4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
4Mb SYNCBURST
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
™
MT58L256L18D, MT58L128L32D,
MT58L128L36D
3.3V V
DD
, 3.3V I/O, Pipelined, Double-Cycle
Deselect
Fast clock and OE# access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
Separate +3.3V isolated output buffer supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and
address pipelining
Clock-controlled and registered addresses, data I/Os
and control signals
Internally self-timed WRITE cycle
Burst control pin (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP package for high density, high speed
119-bump BGA package
Low capacitive bus loading
x18, x32 and x36 versions available
100-Pin TQFP*
119-Bump BGA
OPTIONS
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
256K x 18
128K x 32
128K x 36
• Packages
100-pin TQFP
119-bump, 14mm x 22mm BGA
• Operational Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
MARKING
-6
-7.5
-10
MT58L256L18D
MT58L128L32D
MT58L128L36D
T
B
None
IT
*JEDEC-standard MS-026 BHA (LQFP).
• Part Number Example: MT58L256L18DT-6 IT
GENERAL DESCRIPTION
The Micron
®
SyncBurst
™
SRAM family employs high-
speed, low-power CMOS designs that are fabricated using
an advanced CMOS process.
Micron’s 4Mb SyncBurst SRAMs integrate a 256K x 18,
128K x 32, or 128K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
All synchronous inputs pass through registers controlled
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D.p65 – Rev 9/99
by a positive-edge-triggered single clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
active LOW chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), burst control inputs
(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and
global write (GW#).
Asynchronous inputs include the output enable (OE#),
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved and
linear burst modes. The data-out (Q), enabled by OE#, is
also asynchronous. WRITE cycles can be from one to two
bytes wide (x18) or from one to four bytes wide (x32/x36),
as controlled by the write control inputs.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
All registered and unregistered trademarks are the sole property of their respective companies.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 18
18
SA0, SA1, SA
MODE
ADDRESS
REGISTER
18
16
18
2
SA0-SA1
SA1'
ADV#
CLK
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
SA0'
ADSC#
ADSP#
BYTE “b”
WRITE REGISTER
9
BWb#
BYTE “b”
WRITE DRIVER
9
256K x 9 x 2
MEMORY
ARRAY
9
18
SENSE
18
AMPS
OUTPUT
18
REGISTERS
OUTPUT
BUFFERS
E
18
BWa#
BWE#
GW#
BYTE “a”
WRITE REGISTER
9
BYTE “a”
WRITE DRIVER
DQs
DQPa
DQPb
CE#
CE2
CE2#
OE#
ENABLE
REGISTER
18
PIPELINED
ENABLE
2
INPUT
REGISTERS
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
17
SA0, SA1, SA
ADDRESS
REGISTER
17
15
SA0-SA1
17
MODE
ADV#
CLK
Q1
SA1'
BINARY
COUNTER
SA0'
CLR
Q0
ADSC#
ADSP#
BWd#
BYTE “d”
WRITE REGISTER
BYTE “d”
WRITE DRIVER
BYTE “c”
WRITE DRIVER
BYTE “b”
WRITE DRIVER
BYTE “a”
WRITE DRIVER
INPUT
REGISTERS
128K x 8 x 4
(x32)
128K x 9 x 4
(x36)
SENSE
AMPS
BWc#
BYTE “c”
WRITE REGISTER
OUTPUT
REGISTERS
BWb#
BYTE “b”
WRITE REGISTER
MEMORY
ARRAY
OUTPUT
BUFFERS
E
DQs
DQPa
DQPd
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
4
NOTE:
Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and timing
diagrams for detailed information.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D.p65 – Rev 9/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
Burst operation can be initiated with either address status
processor (ADSP#) or address status controller (ADSC#)
inputs. Subsequent burst addresses can be internally
generated as controlled by the burst advance input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE cycles.
Individual byte enables allow individual bytes to be written.
During WRITE cycles on the x18 device, BWa# controls
DQa’s and DQPa; BWb# controls DQb’s and DQPb. During
WRITE cycles on the x32 and x36 devices, BWa# controls
DQa’s and DQPa; BWb# controls DQb’s and DQPb; BWc#
controls DQc’s and DQPc; BWd# controls DQd’s and DQPd.
GW# LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
This device incorporates an additional pipelined enable
register which delays turning off the output buffer an
additional cycle when a deselect is executed. This feature
allows depth expansion without penalizing system
performance.
Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V
V
DD
power supply, and all inputs and outputs are TTL-
compatible. The device is ideally suited for Pentium
®
and
PowerPC pipelined systems and systems that benefit from
a very wide, high-speed data bus. The device is
also ideal in generic 16-, 18-, 32-, 36-, 64- and 72-bit-wide
applications.
Please refer to the Micron Web site (www.micron.com/
mti/msp/html/sramprod.html)
for the latest data sheet.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
NC
NC
NC
x32/x36
NC/DQPc*
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
V
SS
V
DD
Q
NC
DQd
NC
DQd
NC
NC/DQPd*
MODE
SA
SA
SA
SA
SA1
SA0
DNU
DNU
V
SS
V
DD
NF
NF
SA
SA
SA
SA
SA
SA
SA
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa*
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
V
SS
V
DD
Q
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
NC
NC
SA
NC
NC
DQb
DQb
NC
NC
DQb
DQb
DQb
DQb
DQa
DQa
NC
NC
DQb
DQb
DQPb
NC
DQa
DQa
DQPa
NC
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D.p65 – Rev 9/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PIN ASSIGNMENT (Top View)
100-Pin TQFP
(D-1)
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
NC
NC
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/DQPb*
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NC/DQPa*
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DD
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
NC
NC
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D.p65 – Rev 9/99
NC/DQPc*
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NC/DQPd*
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
37
37
36
36
32-35, 44-50, 32-35, 44-50,
80-82, 99,
81, 82, 99,
100
100
93
94
–
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the rising
edge of CLK.
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
87
87
BWE#
Input
88
88
GW#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
64
64
ZZ
Input
97
97
CE2
Input
86
83
86
83
OE#
ADV#
Input
Input
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D.p65 – Rev 9/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
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