74LVC2G86
Dual 2-input exclusive-OR gate
Rev. 03 — 7 February 2005
Product data sheet
1. General description
The 74LVC2G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC2G86 provides the dual 2-input exclusive-OR gate.
2. Features
s
s
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
Inputs accept voltages up to 5 V
Direct interface with TTL levels
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V)
±24
mA output drive (V
CC
= 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
s
s
s
s
s
s
Philips Semiconductors
74LVC2G86
Dual 2-input exclusive-OR gate
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PHL,
t
PLH
propagation delay inputs
nA, nB to outputs nY
Conditions
V
CC
= 1.8 V;
C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V;
C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V;
C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V;
C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V;
C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
[1]
Min
-
-
-
-
-
-
Typ
3.8
2.5
3.0
2.3
1.9
2.5
15.8
Max
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
pF
pF
input capacitance
power dissipation
capacitance per gate
V
CC
= 3.3 V
[1] [2]
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of switching inputs;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
[2]
The condition is V
I
= GND to V
CC
.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74LVC2G86DP
74LVC2G86DC
74LVC2G86GT
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP8
VSSOP8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
×
1.95
×
0.5 mm
Version
SOT505-2
SOT765-1
SOT833-1
Type number
5. Marking
Table 3:
Marking
Marking code
V86
V86
V86
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Type number
74LVC2G86DP
74LVC2G86DC
74LVC2G86GT
9397 750 14506
Product data sheet
Rev. 03 — 7 February 2005
2 of 15
Philips Semiconductors
74LVC2G86
Dual 2-input exclusive-OR gate
6. Functional diagram
1
1
2
5
6
1A
1B
2A
2B
2
1Y
7
5
6
mna737
mna738
=1
7
2Y
3
=1
3
Fig 1. Logic symbol
Fig 2. IEC logic symbol
B
Y
A
mna040
Fig 3. Logic diagram (one driver)
7. Pinning information
7.1 Pinning
86
1A
1A
1B
2Y
GND
1
2
3
4
001aab836
1
8
V
CC
8
7
V
CC
1Y
2B
2A
1B
2
7
1Y
86
6
5
2Y
3
6
2B
GND
4
5
2A
001aab837
Transparent top view
Fig 4. Pin configuration TSSOP8 and
VSSOP8
Fig 5. Pin configuration XSON8
9397 750 14506
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 7 February 2005
3 of 15
Philips Semiconductors
74LVC2G86
Dual 2-input exclusive-OR gate
7.2 Pin description
Table 4:
Symbol
1A
1B
2Y
GND
2A
2B
1Y
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
1 data input A
1 data input B
2 data output Y
ground (0 V)
2 data input A
2 data input B
1data output Y
supply voltage
8. Functional description
8.1 Function table
Table 5:
Input
nA
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output
nB
L
H
L
H
nY
L
H
H
L
9397 750 14506
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 7 February 2005
4 of 15
Philips Semiconductors
74LVC2G86
Dual 2-input exclusive-OR gate
9. Limiting values
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
,
I
GND
T
stg
P
tot
[1]
[2]
Conditions
[1]
Min
−0.5
−0.5
−0.5
−0.5
-
-
-
-
−65
Max
+6.5
+6.5
+6.5
−50
±50
±50
±100
+150
300
Unit
V
V
V
mA
mA
mA
mA
°C
mW
supply voltage
input voltage
output voltage
input diode current
output diode current
output source or sink
current
V
CC
or GND current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
Active mode
Power-down mode
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[1]
[1] [2]
V
CC
+ 0.5 V
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
10. Recommended operating conditions
Table 7:
V
CC
V
I
V
O
Recommended operating conditions
Conditions
Min
1.65
0
Active mode
Power-down mode;
V
CC
= 0 V
T
amb
t
r
, t
f
ambient temperature
input rise and fall
times
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
0
0
−40
0
0
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
supply voltage
input voltage
output voltage
Symbol Parameter
9397 750 14506
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 7 February 2005
5 of 15
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