CD40718, CD40728, CD40758 Typ
s
COS/MOS OR Gates
High-Voltage Types (20-Volt Rating)
CD40718 Quad 2-lnput OR Gate
CD40728 Dual 4-lnput OR Gate
CD40758 Triple 3-lnput OR Gate
The RCA-C04071 B, C04072B, and
CD4075B OR gates provide the system
designer with direct implementation of the
positive-logic OR function and supplement
the existing family of COS/MaS gates. The
CD4071, CD4072, and C04075 types are
supplied in 14-lead dual-in-line ceramic
packages (0 and F suffixes), 14-lead dual-
in-line plastic packages (E suffix), 14-lead
ceramic flat packages (K suffix), and in chip
form (H suffix).
Features:
• Nledium-Speed Operation-tpLH'
tpHL = 60 ns (typ.) at VDD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current
of
1 J.1.A at 18 V
over full package-temperature range; 100 nA at
18 V and 25
0
C
• Standardized, symmetrical output characteristics
• Noise margin (over full package temperature
range)
1 Vat VDD = 5 V
2 V at VDD = 10 V
2.5 Vat VDD = 15 V
• 5·V, 10-V, and 16-V parametric ratings
• Meets all requirements of JEDEC Tenta·
tive Stilndard
~o.
13 A, "Standard
Specifications for Description of
'B'
Series
CMOS Devices"
VOD
3
J
4 K
F B
E 9
H 12
'0 L
II
G 13
..
Vss
CD4071B
FUNCTIONAL DIAGRAM
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
I
MAX.
Supply· Voltage Range (For T A
=
Full Package·Temperature
3
18
V
Range)
o
E
F
10
I
G "
H
12
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES (OCI
Valuesat-55,+25,+125 Apply to D:F,H Packages
Values at
-40,
+25, +85 Apply to E Package
CHARACTER-
ISTIC
CONDITIONS
Vo
(VI
CD4072B
FUNCTIONAL DIAGRAM
UNITS
Quiescent Device
Current,
100 Max.
-
-
-
-
VIN VDD
(VI -55
(VI
5
0.25
0,5
0,10 10
0.5
0,15 15
1
0,20
0,5
0,10
015
0,5
0,5
0,10
0,15
0,5
0,10
0,15
0,5
0,10
0,15
20
5
10
15
5
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
18
to.l
-40
0.25
0.5
1
5
+85
7.5
15
+125
7.5
15
Min.
+25
Typ.
0.Q1
0.01
0.01
0.02
1
26
6.8
-1
-3.2
-2.6
-;-68
0
0
0
5
10
15
Max.
0.25
0.5
1
5
p.A
9
J
Output Low
(Sink) Current
IOLMin.
Output High
(Source)
Current,
IOH Min.
Output Voltage:
Low-Level,
VOL Max.
Output Voltage:
High-Level,
VOH Min.
Input Low
Voltage,
VI~
Max.
Input High
Voltage,
VIH Min.
Input Current
liN Max.
0.4
0.5
1.5
4.6
2.5
9.5
13.5
30
5
150
0.42
0.64 0.61
1.1
1.6
1.5
4
2.8
4.2
-0.64 -0.61 -0.42
-1.3
-2
-1.8
-1.1
-1.6 -1.5
-4
-2.8
-4.2
0.05
0.05
005
4.95
9.95
14.95
1.5
3
4
3.5
7
11
to.l
tl
30
150
0.36 0.51
0.9
1.3
2.4
34
-0.36 -0.51
-1.15 -1.6
-0.9 -13
-2.4 -3.4
-
-
-
-
-
-
-
-
mA
10
L
-
-
-
0.05
0.05
0.05
-
-
-
-
-
-
4.95
9.95
14.95
-
-
-
0.5,4.5
1,9
1.5,13.5
4.5
9
13.5
-
-
-
1.5
3
4
V
CD4075B
FUNCTIONAL DIAGRAM
-
-
-
-
-
-
-
3.5
7
11
tl
-
-
-
-
-
-
0,18
-
-
t10- 5
-
-
-
V
-
±0.1
p.A
238 ________________________________________________________________________
CD4071B, CD4072B, CD4075B Typ
s
MAXIMUM IRATINGS,
Absolute-Maximum Values:
DC SUPPLY-\'OLTAGE RANGE, (VDD'
(Voltages relerenced to VSS Terminal)
-0.5 to +20 V
INPUT
VOLT~GE
RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
±10mA
POWER DISSIPATION PER PACKAGE (POl:
Fcn TA -40 to +60 o C (PACKAGE TYPE EI
..
......
500mW
Fc)r T A +60 to +85
0
C (PACKAGE TYPE EI
Derate Linearly at 12 mWf'C to 200 mW
0
C (PACKAGE TYPES D,FI
For T A -!15 to +100
..
.....
500mW
For T A
c
+t 00 to +125
0
C (PACKAGE TYPES 0, FI
Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A
=
fULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
100mW
OPERATING·TEMPERATURE RANGE (TAl
PACKAGE TYPES 0, F, H
-55 to +125
0
C
PACKAGE TYPE E .
-40 to +85
0
C
-65 to +150
0
C
STORAGE TE.MPERATURE RANGE (Tstgl
LEAD TEMPE"RATURE (DURING SOLDERINGI
At d'stance 1/16
±
1/32 Inch (1.59 ± 0 79 mml from case fOI 10 s max.
C
C
C
INPUT VOLTAGE (V,N' - v
Fig.
1 -
Typical voltage transfer
characteristics.
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf = 20 ns,
and CL = 5(] pF, RL
=;
200
kn
TEST CONDITI
or
~S
ALL TYPES
LIMITS
TYP.
125
60
45
100
50
40
5
MAX.
250
120
90
200
100
80
CHA
RACTERISTIC
,-
,
Ie
Propagat Ion Delay Time,
':PHl' tplH
Transltio n Time,
tTHl' tTlH
Input
Ca~
,acitance,
v
DO
ILTS
5
10
'15
5
'10
'15
UNITS
ns
ns
pF
lOAD CAPACITANCE (ClI-.F
CIN
Any Input
VDD
,-
Fig.
2 -
TYPical propagation delay time
as a function of/oad capacitance.
7.5
*
All
COSIMOS
ARE PROTECTED
INPUTS
BY
PROTECTION
NETWORK
Fig.
3 -
Schematic diagram for CD40118 (1of
4
Identical gates).
a
- ---
"ss
DD
,
DRAIN-TO-SOURCE VOLTAGE IVDSI-v
92CS·29114
"ss
FIg.
4 -
Typical output low (sink) current
character/stics.
1(6'8'131~r--~ ~
A
l/~ ~3(4,IO,1I1
2 (5,9,121
92CIi-291l9
DRAIN-TO-SOURCE VOLTAGE
lVosl-V
Fig.
6 -
Fig.
5 -
Logic diagram for CD40118 (1of
4
Identical gates).
Minimum output low (sink) current
characteristics.
__________________---------------------------239
CD4071B, CD4072B, CD4075B Typ
s
DIIAIN-lD-SOURCE VOLTAGE IVoS)-V
INV I ·
Vss
,5
---
2 (12)
3 (11)
6 (9)
YOO
'1'U-l4.J201.)
*
BY COS'MOS ARE PROTECTEO
ALL INPUTS
PROTECTION
NETWORK
VSS
Fig.
8 -
Typical output high (source) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE IVDSI-V
Fig.
7 -
Schematic diagram for CD40728
(1
of
2
identical gates).
11131
4 (10)
Fig. 9
-
Logic diagram for CD40728
(1
of
2
identical gates).
Fig. 10
-
Minimum output high (source) current
charactf!,istics.
.,.,,,:-1
2 (4,'2)0----4-..
1
(3,11)O*---+---~
VS:
*
BY COS 'MOS ARE PROTECTEO
ALL INPUTS
PROTECTION
NETWORK
,5--
Fig.
12 -
Typical transition tim.e as a function
of loed capacitance.
Yoo
VSS
~2C" ·2911~
Fig.
11 -
Schematic diagram for CD40758
(1
of
3
identical gates).
.
-
·
-
.
00":
I
_£NT
TlIll'EllATUII[ IT
A -25·C
...
:- 10".
~IQ!
~
i
Fig.
13 -
Logic diagram for CD40758
(1
of
3
identical gates).
~
III()2
i
--'!l
·
-
·
I
-
!
I
h
IV
1//
1//
V
","'~V
T
~IV
VI-'
I
,,~
V
/1;
~
I7l,.?oIY~
~
//
CL·~
p'
CL'15
of ---
10'
'NPUT
fREQU[NCY
(0
1 ' -
.H,
'0
i'
II
IQ!
I
I
I
••
Fig.
14 -
Typical dyanamic power dissipation
as a function
o(
frequency.
'0-.
. ,
240 _____________________________________________________________________
CD4071B, CD4072B, CD4075B Typ
s
TERMINAL ASSIGNMENTS (TOP VIEW)
INPUTS
B-
J-A+B-
K"C+O-
C-
VSS-
'[
2
3
4
o
14
13
12
II
10
9
VOO
H
0
""O+H
L"E+F
XC
Vss
J"A+B+C+O
I.
2
14
13
12
o
:I
6
C04CI7IB
.2CS-24"'4
10
6
9
7
B
CD4072B
Voo
K"E+I'+II+H
H
0
F
E
XC
92CS-l""96RI
Vss
o
VOO
K"O+E+F
L"O+H+X
J "A+B+C
VSS
-"'L..-_.llr-C
CD4D7!18
92CS-244'"
DO
Vss
9ZCS-zr4l0IAI
XC" INTERNAL CONNECTION
DO
NOT USE
FIg.
15 -
OUlescent device current test circuIt.
V~.P(JU' :::;".,,~
,~
o
""""'..::.,r-
Vss
SEOUENTIALLY.
TO BOTH VOO
AND
VSS
CONNECT ALL UNUSED
INPUTS
TO
EITHER
VOO CRV
SS
VSS
92C5-27402
Fig.
16 -
Input current test circuit.
vs.~UT·O·'~'~
,~
v
1L
•
.J
NOTE
Vss
92CS-Z144" I
~srN'p~~0M8INATI()N
Fig.
17 -
Input-voltage test circuit.
D,menslollS
.n
parentheses are
.n
mll.',meters and
are deflved from the baSIC .nch d""e.1slOns as
.n.
d,cated Gfld graduatIons are
.n
mils (10- 3 .nch)
The photographs and d,menSIons of
t~ach
CDSIMDS
chIp represent a chIp when It IS part of the wafer
When the
w~fer
IS cut Into"
ChIP~,
the cleavage
angles are
57
Instead of 90 with respect to the
face of the chIp Therefore, the nola ted chIp IS
actually
7
mils (0
17
mm) larger In both dImenSIons
'2eS-2'1I1
DImensions and pad layout for CD4071 B.
.aU-HI 10
Dimensions and pad layout for CD4072B.
DimensIons and pad layout for CD4075B.
___________________________________________ 241
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