Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> RN80532KC0682M

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RN80532KC0682M: 产品描述RISC Microprocessor, 32-Bit, 2700MHz, CMOS, CPGA603; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小2MB，共126页; 制造商Intel(英特尔); 官网地址http://www.intel.com/

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RN80532KC0682M概述

RISC Microprocessor, 32-Bit, 2700MHz, CMOS, CPGA603

RN80532KC0682M规格参数

参数名称	属性值
是否Rohs认证	不符合
Objectid	2072938246
包装说明	SPGA, PGA603,25X31,50
Reach Compliance Code	unknown
ECCN代码	3A991.A.1
位大小	32
JESD-30 代码	R-XPGA-P603
JESD-609代码	e0
端子数量	603
封装主体材料	CERAMIC
封装代码	SPGA
封装等效代码	PGA603,25X31,50
封装形状	RECTANGULAR
封装形式	GRID ARRAY, SHRINK PITCH
电源	1.5,3.3 V
认证状态	Not Qualified
速度	2700 MHz
表面贴装	NO
技术	CMOS
端子面层	Tin/Lead (Sn/Pb)
端子形式	PIN/PEG
端子节距	1.27 mm
端子位置	PERPENDICULAR
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC

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Intel® Xeon™ Processor MP with up to 4MB L3 Cache (on the 0.13 Micron Process)

Datasheet

Product Features

■

Available at 1.50, 1.90, 2, 2.50, 2.80, and

3 GHz

Multi-processing server support

Binary compatible with applications

running on previous members of the Intel

IA32 microprocessor line

Intel

NetBurst™ microarchitecture

Hyper-Threading Technology

— Hardware support for multi-threaded

applications

■

400 MHz System bus

— Bandwidth up to 3.2 GB/second

512

KB Advanced Transfer L2 Cache (on-

die, full speed Level 2 cache) with 8-way

associativity and Error Correcting Code

(ECC)

1-MB ,2-MB or 4-MB L3 Cache (on-die,

full speed Level 3 cache) with 8-way

associativity and Error Correcting Code

(ECC)

Enables system support of up to 64 GB of

physical memory

Streaming SIMD Extensions 2 (SSE2)

— 144 new instructions for double-precision

floating point operations, media/video

streaming, and secure transactions

■

Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor

core frequency

Hyper-Pipelined Technology

Advance Dynamic Execution

— Very deep out-of-order execution

— Enhanced branch prediction

■

Enhanced floating point and multimedia

unit for enhanced video, audio, encryption,

and 3D performance

Power Management capabilities

— System Management mode

— Multiple low-power states

■

Level 1 Execution Trace Cache stores 12 K

micro-ops and removes decoder latency

from main execution loops

— Includes 8- KB Level 1 data cache

■

Advanced System Management Features

— System Management Bus

— Processor Information ROM (PIROM)

— OEM Scratch EEPROM

— Thermal Monitor

— Machine Check Architecture (MCA)

The Intel

Xeon™ processor MP with up to 4

MB L3 cache on the 0.13 micron process is designed for high-

performance multi-processor server applications. Based on the Intel

NetBurst™ microarchitecture and the new

Hyper-Threading Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The Intel

Xeon processor MP with up to 2

MB L3 cache is scalable to four processors in a multiprocessor system providing

exceptional performance for applications running on advanced operating systems such as Microsoft Windows* XP

and Windows* 2000 operating systems, Linux*, and UNIX*. The Intel Xeon processor MP with up to 4-MB L3

cache delivers compute power at unparalleled value and flexibility for internet infrastructure and departmental

server applications. The Intel NetBurst microarchitecture and Hyper-Threading Technology deliver outstanding

performance and headroom for peak internet server workloads, resulting in faster response times, support for more

users, and improved scalability.

Document Number 251931-003

March 2004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS

OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL

ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO

SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A

PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

The Intel

Xeon

™

processor MP with up to 2-MB L3 Cache may contain design defects or errors known as errata which may

cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed

by Intel. Implementations of the I

C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including

Philips Electronics N.V. and North American Philips Corporation.

Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or its

subsidiaries in the United States and other countries.

* Other names and brands may be claimed as the property of others.

Intel® Xeon™ Processor MP with up to 4-MB L3 Cache

Contents

Introduction

............................................................................................................................. 1-1

1.1

1.2

Terminology .................................................................................................................... 1-3

1.1.1

Processor Packaging Terminology.................................................................... 1-3

References ....................................................................................................................... 1-4

System Bus and GTLREF ............................................................................................... 2-1

Power and Ground Pins ................................................................................................... 2-1

Decoupling Guidelines .................................................................................................... 2-1

2.3.1

VCC Decoupling ............................................................................................... 2-2

2.3.2

System Bus AGTL+ Decoupling ...................................................................... 2-2

System Bus Clock (BCLK[1:0]) and Processor Clocking .............................................. 2-2

2.4.1

Bus Clock......................................................................................................... 2-3

PLL Filter ........................................................................................................................ 2-4

2.5.1

Mixing Processors............................................................................................. 2-5

Voltage Identification..................................................................................................... 2-6

2.6.1

Mixing Processors of Different Voltages.......................................................... 2-7

Reserved or Unused Pins................................................................................................. 2-8

System Bus Signal Groups .............................................................................................. 2-8

Asynchronous GTL+ Signals .......................................................................................... 2-9

Maximum Ratings ......................................................................................................... 2-10

Processor DC Specifications ......................................................................................... 2-10

AGTL+ System Bus Specifications .............................................................................. 2-17

System Bus AC Specifications...................................................................................... 2-18

Processor AC Timing Waveforms................................................................................. 2-23

System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines 3-

System Bus Signal Quality Specifications and Measurement Guidelines ...................... 3-2

System Bus Signal Quality Specifications and Measurement Guidelines ...................... 3-5

3.3.1

Overshoot/Undershoot Guidelines.................................................................... 3-5

3.3.2

Overshoot/Undershoot Magnitude.................................................................... 3-6

3.3.3

Overshoot/Undershoot Pulse Duration ............................................................. 3-6

3.3.4

Activity Factor .................................................................................................. 3-6

3.3.5

Reading Overshoot/Undershoot Specification Tables ...................................... 3-7

3.3.6

Determining if a System Meets the Overshoot/Undershoot Specifications...... 3-7

Mechanical Specifications............................................................................................... 4-3

Package Load Specifications........................................................................................... 4-8

Insertion Specifications ................................................................................................... 4-8

Mass Specifications ......................................................................................................... 4-8

Materials .......................................................................................................................... 4-9

Markings.......................................................................................................................... 4-9

Pinout Diagram.............................................................................................................. 4-10

Electrical Specifications

...................................................................................................... 2-1

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

System Bus Signal Quality Specifications

.................................................................... 3-1

3.1

3.2

3.3

Mechanical Specifications

.................................................................................................. 4-1

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Intel® Xeon™ Processor MP with up to 4-MB L3 Cache

iii

Thermal Specifications

........................................................................................................ 5-1

5.1

5.2

Thermal Specifications .................................................................................................... 5-3

Measurements for Thermal Specifications ...................................................................... 5-5

5.2.1

Processor Case Temperature Measurement ...................................................... 5-5

Power-On Configuration Options.................................................................................... 6-1

Clock Control and Low Power States.............................................................................. 6-1

6.2.1

Normal State—State 1....................................................................................... 6-1

6.2.2

AutoHALT Powerdown State—State 2 ............................................................ 6-1

6.2.3

Stop-Grant State—State 3 ................................................................................. 6-2

6.2.4

HALT/Grant Snoop State—State 4................................................................... 6-3

6.2.5

Sleep State—State 5 .......................................................................................... 6-3

6.2.6

Bus Response during Low Power States........................................................... 6-4

Thermal Monitor.............................................................................................................. 6-4

6.3.1

Thermal Diode................................................................................................... 6-4

System Management Bus (SMBus) Interface ................................................................. 6-5

6.4.1

Processor Information ROM (PIROM)............................................................. 6-6

6.4.2

Scratch EEPROM.............................................................................................. 6-8

6.4.3

PIROM and Scratch EEPROM Supported SMBus Transactions ..................... 6-8

6.4.4

SMBus Thermal Sensor .................................................................................... 6-8

6.4.5

Thermal Sensor Supported SMBus Transactions.............................................. 6-9

6.4.6

SMBus Thermal Sensor Registers................................................................... 6-11

6.4.6.1 Thermal Reference Registers............................................................ 6-11

6.4.6.2 Thermal Limit Registers ................................................................... 6-11

6.4.6.3 Status Register .................................................................................. 6-11

6.4.6.4 Configuration Register...................................................................... 6-12

6.4.6.5 Conversion Rate Registers................................................................ 6-13

6.4.7

SMBus Thermal Sensor Alert Interrupt .......................................................... 6-13

6.4.8

SMBus Device Addressing ............................................................................. 6-13

Introduction ..................................................................................................................... 7-1

Mechanical Specifications ............................................................................................... 7-2

7.2.1

Boxed Processor Heatsink Dimensions............................................................. 7-2

7.2.2

Boxed Processor Heatsink Weight.................................................................... 7-2

7.2.3

Boxed Processor Retention Mechanism and Heatsink Supports ...................... 7-2

Boxed Processor Requirements ....................................................................................... 7-5

7.3.1

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor....................

........................................................................................................................... 7-5

Thermal Specifications .................................................................................................... 7-5

7.4.1

Boxed Processor Cooling Requirements........................................................... 7-5

Logic Analyzer Interface (LAI)....................................................................................... 8-1

8.1.1

Mechanical Considerations ............................................................................... 8-1

8.1.2

Electrical Considerations................................................................................... 8-1

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor Pin Assignments . 9-1

9.1.1

Pin Listing by Pin Number.............................................................................. 9-10

Signal Definitions .......................................................................................................... 9-19

Intel® Xeon™ Processor MP with up to 4-MB L3 Cache

Features

...................................................................................................................................... 6-1

6.1

6.2

6.3

6.4

Boxed Processor Specifications

........................................................................................ 7-1

7.1

7.2

7.3

7.4

Debug Tools Specifications

......................................................................................... 8-1

8.1

Pin Listing and Signal Definitions

........................................................................... 9-1

9.1

9.2

Figures

Typical VCCIOPLL, VCCA and VSSA Power Distribution.......................................... 2-4

Phase Lock Loop (PLL) Filter Requirements ................................................................. 2-5

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor Voltage-Current Pro-

jections (1.5V) ............................................................................................................... 2-12

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor Voltage-Current Pro-

jections (1.475 VID)...................................................................................................... 2-13

Electrical Test Circuit.................................................................................................... 2-23

TCK Clock Waveform .................................................................................................. 2-24

Differential Clock Waveform........................................................................................ 2-24

Differential Clock Crosspoint Specification ................................................................. 2-25

System Bus Common Clock Valid Delay Timing Waveform ...................................... 2-25

System Bus Source Synchronous 2X (Address) Timing Waveform............................. 2-26

System Bus Source Synchronous 4X (Data) Timing Waveform .................................. 2-27

System Bus Reset and Configuration Timing Waveform ............................................. 2-28

Power-On Reset and Configuration Timing Waveform................................................ 2-28

TAP Valid Delay Timing Waveform ............................................................................ 2-29

Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform.......... 2-29

THERMTRIP# to Vcc Timing ...................................................................................... 2-29

SMBus Timing Waveform ............................................................................................ 2-30

SMBus Valid Delay Timing Waveform........................................................................ 2-30

Example 3.3 Volt/SM_VCC Sequencing ...................................................................... 2-31

FERR#/PBE# Valid Delay Timing ............................................................................... 2-32

BCLK[1:0] Signal Integrity Waveform........................................................................... 3-2

Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous

GTL+ Buffers3-3

High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous

GTL+ Buffers3-3

Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers

3-4

High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers

3-5

Maximum Acceptable Overshoot/Undershoot Waveform............................................ 3-10

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel

Xeon™ Pro-

cessor with 512-KB L2 Cache in INT-mPGA Package - Assembly Drawing (Including

Socket)............................................................................................................................. 4-2

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor Package Top View

Component Placement Detail .......................................................................................... 4-3

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor Package Drawing 4-3

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor Top View - Compo-

nent Keep-In .................................................................................................................... 4-5

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel

Xeon™ Pro-

cessor with 512-KB L2 Cache in INT-mPGA Package - Cross Section View - Pin Side

Component Keep-In ........................................................................................................ 4-5

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel

Xeon™ Pro-

cessor with 512-KB L2 Cache in INT-mPGA Package - Processor Pin Details............. 4-6

Intel

Xeon™ Processor MP on the 0.13 Micron Process Processor Package IHS Flatness

and Tilt Drawing.............................................................................................................. 4-7

Intel® Xeon™ Processor MP on the 0.13 Micron Process INT-mPGA Package IHS Flat-

ness and Tilt Drawing...................................................................................................... 4-7

Intel® Xeon™ Processor MP with up to 4-MB L3 Cache

RN80532KC0682M

RN80532KC0682M概述

RN80532KC0682M规格参数

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