MO2019
High Frequency, High Temp, One-output Clock Generator
Features
Applications
Frequencies between 115.194001 MHz to 137 MHz accurate to 6
decimal places
Operating temperature from -40°C to +125°C. For -55°C option,
refer to MO2020 and MO2021
Supply voltage of +1.8V or +2.5V to +3.3V
Excellent total frequency stability as low as ±20 ppm
Low power consumption of +4.9 mA typical at 125 MHz, +1.8V
LVCMOS/LVTTL compatible output
5-pin SOT23-5 package: 2.9mm x 2.8mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 clock generators, refer to MO2024 and MO2025
Industrial, medical, avionics and other high temperature applica-
tions
Industrial sensors, PLC, motor servo, outdoor networking
equipment, medical video cam, asset tracking systems, etc.
Electrical Specifications
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values
are at +25°C and nominal supply voltage.
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Range
Output Frequency Range
f
115.194001
–
137
MHz
Refer to
Table 14
for the exact list of supported frequencies
list of supported frequencies
Frequency Stability and Aging
-20
Frequency Stability
F_stab
-25
-30
-50
-40
-40
+1.62
+2.25
Supply Voltage
Vdd
+2.52
+2.7
+2.97
+2.25
–
Current Consumption
Idd
–
–
OE Disable Current
I_od
–
–
–
Standby Current
I_std
–
–
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
–
–
–
–
–
–
+1.8
+2.5
+2.8
+3.0
+3.3
–
+6.2
+5.4
+4.9
–
–
+2.6
+1.4
+0.6
–
1.0
1.3
1.0
–
+20
+25
+30
+50
+105
+125
+1.98
+2.75
+3.08
+3.3
+3.63
+3.63
+8.0
+7.0
+6.0
+4.8
+4.5
+8.5
+5.5
+4.0
55
2.0
2.5
3.0
–
ppm
ppm
ppm
ppm
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
mA
μA
μA
μA
%
ns
ns
ns
Vdd
No load condition, f = 125 MHz, Vdd = +2.8V, +3.0V or +3.3V
No load condition, f = 125 MHz, Vdd = +2.5V
No load condition, f = 125 MHz, Vdd = +1.8V
Vdd = +2.5V to +3.3V, OE = Low, Output in high Z state.
Vdd = +1.8V, OE = Low, Output in high Z state.
Vdd = +2.8V to +3.3V,
ST
= Low, Output is weakly pulled down
Vdd = +2.5V,
ST
= Low, Output is weakly pulled down
Vdd = +1.8V,
ST
= Low, Output is weakly pulled down
All Vdds
Vdd = +2.5V, +2.8V, +3.0V or +3.3V, 20% - 80%
Vdd = +1.8V, 20% - 80%
Vdd = +2.25V - +3.63V, 20% - 80%
IOH = -4.0 mA (Vdd = +3.0V or +3.3V)
IOH = -3.0 mA (Vdd = +2.8V or +2.5V)
IOH = -2.0 mA (Vdd = +1.8V)
IOL = +4.0 mA (Vdd = +3.0V or +3.3V)
IOL = +3.0 mA (Vdd = +2.8V or +2.5V)
IOL = +2.0 mA (Vdd = +1.8V)
Extended Industrial
Automotive
Inclusive of Initial tolerance at +25°C, 1st year aging at +25°C,
and variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Operating Temperature Range
Operating Temperature Range
(ambient)
T_use
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Daishinku Corp.
Rev. 1.01
1389 Shinzaike, Hiraoka-cho, Kakogawa, Hyogo 675-0194 Japan
+81-79-426-3211
www.kds.info
Revised September 29, 2015
MO2019
High Frequency, High Temp, One-output Clock Generator
Table 1. Electrical Characteristics (continued)
Parameters
Symbol
VIH
VIL
Z_in
Min.
70%
–
50
2.0
–
–
–
–
–
–
–
–
–
Typ.
–
–
87
–
–
–
–
1.6
1.8
12
14
0.5
1.3
Max.
–
30%
150
–
5.0
130
5.0
Jitter
RMS Period Jitter
T_jitt
2.5
3.0
20
30
0.8
2.0
ps
ps
ps
ps
ps
ps
f = 125 MHz, Vdd = +2.5V, +2.8V, +3.0V or +3.3V
f = 125 MHz, Vdd = +1.8V
f = 125 MHz, Vdd = +2.5V, +2.8V, +3.0V or +3.3V
f = 125 MHz, Vdd = +1.8V
f = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 125 MHz, Integration bandwidth = 12 kHz to 20 MHz
Unit
Vdd
Vdd
kΩ
MΩ
ms
ns
ms
Condition
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedence
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Measured from the time Vdd reaches its rated minimum value
f = 115.194001 MHz. For other frequencies, T_oe = 100 ns + 3 *
clock periods
Measured from the time
ST
pin crosses 50% threshold
Startup and Resume Timing
Startup Time
Enable/Disable Time
Resume Time
T_start
T_oe
T_resume
Peak-to-peak Period Jitter
T_pk
RMS Phase Jitter (random)
T_phj
Table 2. Pin Description
Pin
1
2
Symbol
GND
NC
Power
No Connect
Output
Enable
3
OE/ ST/NC
Standby
Electrical ground
No connect
H
[1]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[1]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Any voltage between 0 and Vdd or Open
[1]
: Specified frequency
output. Pin 3 has no function.
Power supply voltage
Oscillator output
[2]
Top View
Functionality
OE/ST/NC NC
3
2
GND
1
No Connect
4
5
Notes:
VDD
OUT
Power
Output
4
5
VDD
OUT
Figure 1. Pin Assignments
1. In OE or
ST
mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven.
If pin 3 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev. 1.01
Page 2 of 12
www.kds.info
MO2019
High Frequency, High Temp, One-output Clock Generator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the
IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[3]
Min.
-65
-0.5
–
–
–
Max.
+150
+4.0
+2000
+260
+150
Unit
°C
V
V
°C
°C
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[4]
Package
SOT23-5
JA
, 4 Layer Board
(°C/W)
421
JC
, Bottom
(°C/W)
175
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[5]
Max Operating Temperature (ambient)
+105°C
+125°C
Maximum Operating Junction Temperature
+115°C
+135°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.01
Page 3 of 12
www.kds.info
MO2019
High Frequency, High Temp, One-output Clock Generator
Test Circuit and Waveform
[6]
Test
Point
Vout
Vdd
Tr
5
4
0.1µF
Power
Supply
Tf
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
15pF
(including probe
and fixture
capacitance)
1
2
3
Vdd
1k
OE/STFunction
Figure 2. Test Circuit
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Output Waveform
Timing Diagrams
Vdd
50% Vdd
Vdd
90% Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[7]
ST Voltage
T_resume
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ST Mode)
Figure 5. Standby Resume Timing (ST Mode Only)
Vdd
50% Vdd
T_oe
OE Voltage
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Figure 7. OE Disable Timing (OE Mode Only)
Note:
7. MO2019 has “no runt” pulses and “no glitch” output during startup or resume.
Rev. 1.01
Page 4 of 12
www.kds.info
MO2019
High Frequency, High Temp, One-output Clock Generator
Performance Plots
[8]
1.8
6.5
6.3
6.1
5.9
5.7
2.5
2.8
3.0
3.3
DUT1
DUT8
DUT15
25
20
DUT2
DUT9
DUT16
DUT3
DUT10
DUT17
DUT4
DUT11
DUT18
DUT5
DUT12
DUT19
DUT6
DUT13
DUT20
DUT7
DUT14
Frequency (ppm)
117
119
121
123
125
127
129
131
133
135
137
15
10
5
0
-5
-10
-15
-20
-25
‐55
‐35
‐15
5
25
45
65
85
105
125
Idd (mA)
5.5
5.3
5.1
4.9
4.7
4.5
115
Frequency (MHz)
Temperature (°C)
Figure 8. Idd vs Frequency
Figure 9. Frequency vs Temperature
1.8 V
4.0
3.5
2.5 V
2.8 V
3.0 V
3.3 V
55
54
53
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
RMS period jitter (ps)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
115
117
119
121
123
125
127
129
131
133
135
137
Duty cycle (%)
52
51
50
49
48
47
46
45
115
117
119
121
123
125
127
129
131
133
135
137
Frequency (MHz)
Frequency (MHz)
Figure 10. RMS Period Jitter vs Frequency
Figure 11. Duty Cycle vs Frequency
1.8 V
2.5
2.5 V
2.8 V
3.0 V
3.3 V
2.5
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
2.0
2.0
Rise time (ns)
1.5
Fall time (ns)
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90 100 110
120
1.5
1.0
1.0
0.5
0.5
0.0
0.0
-55 -45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Temperature (°C)
Temperature (°C)
Figure 12. 20%-80% Rise Time vs Temperature
(125 MHz Output)
Figure 13. 20%-80% Fall Time vs Temperature
(125 MHz Output)
Rev. 1.01
Page 5 of 12
www.kds.info
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
