PROFET® BTS 432 E2
Smart Highside Power Switch
•
Load dump and reverse battery protection
1)
•
Clamp of negative voltage at output
•
Short-circuit protection
•
Current limitation
•
Thermal shutdown
•
Diagnostic feedback
•
Open load detection in ON-state
•
CMOS compatible input
•
Electrostatic discharge
(ESD) protection
•
Loss of ground and loss of V
bb
protection
2)
•
Overvoltage protection
•
Undervoltage and overvoltage shutdown with auto-
restart and hysteresis
Features
Product Summary
80
V
Load dump
V
bb
-V
OUT
Avalanche Clamp
58
V
bb (operation)
4.5 ... 42
V
bb (reverse)
-32
R
ON
38
I
L(SCp)
44
I
L(SCr)
35
I
L(ISO)
11
V
V
V
V
mΩ
A
A
A
5
1
Straight leads
1
5
5
Application
• µC
compatible power switch with diagnostic feedback
for 12 V and 24 V DC grounded loads
•
All types of resistive, inductive and capacitve loads
•
Replaces electromechanical relays and discrete circuits
SMD
Standard
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, integrated in Smart SIPMOS chip on chip technology. Providing protective functions.
R bb
+ V bb
Voltage
source
V
Logic
Voltage
sensor
3
Overvoltage
protection
Current
limit
Gate
protection
OUT
Charge pump
Level shifter
Rectifier
Limit for
unclamped
ind. loads
Open load
2
IN
Temperature
sensor
5
ESD
Logic
Load
detection
Short circuit
detection
GND
4
ST
PROFET
Load GND
1
Signal GND
1)
2)
No external components required, reverse load current limited by connected load.
Additional external diode required for charged inductive loads
Semiconductor Group
1 of 14
2003-Oct-01
BTS 432 E2
Pin
1
2
3
4
5
Symbol
GND
IN
Vbb
ST
OUT
(Load, L)
-
I
+
S
O
Function
Logic ground
Input, activates the power switch in case of logical high signal
Positive power supply voltage,
the tab is shorted to this pin
Diagnostic feedback, low on failure
Output to the load
Maximum Ratings
at T
j
= 25 °C unless otherwise specified
Parameter
Supply voltage (overvoltage protection see page 3)
Load dump protection
V
LoadDump
=
U
A
+
V
s
,
U
A
= 13.5 V
R
I
= 2
Ω,
R
L
= 1.1
Ω,
t
d
= 200 ms, IN= low or high
Load current (Short-circuit current, see page 4)
Operating temperature range
Storage temperature range
Power dissipation (DC)
Inductive load switch-off energy dissipation,
single pulse
T
j
=150 °C:
Electrostatic discharge capability (ESD)
(Human Body Model)
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagrams page 6...
Symbol
V
bb
V
s3
)
I
L
T
j
T
stg
P
tot
E
AS
V
ESD
V
IN
I
IN
I
ST
Values
63
66.5
self-limited
-40 ...+150
-55 ...+150
125
1.7
2.0
-0.5 ... +6
±5.0
±5.0
≤
1
≤
75
≤
tbd
Unit
V
V
A
°C
W
J
kV
V
mA
Thermal resistance
chip - case:
junction - ambient (free air):
SMD version, device on pcb
4)
:
R
thJC
R
thJA
K/W
3)
4
)
V
S
is setup without DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
Semiconductor Group
2
2003-Oct-01
BTS 432 E2
Electrical Characteristics
Parameter and Conditions
at T
j
= 25 °C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Load Switching Capabilities and Characteristics
On-state resistance (pin 3 to 5)
I
L
= 2 A
T
j
=25 °C:
R
ON
T
j
=150 °C:
Nominal load current (pin 3 to 5)
ISO Proposal:
V
ON
= 0.5 V,
T
C
= 85 °C
Output current (pin
5
) while GND disconnected or
GND pulled up, V
IN
= 0, see diagram page 7,
T
j
=-40...+150°C
Turn-on time
to 90%
V
OUT
:
Turn-off time
to 10%
V
OUT
:
R
L
= 12
Ω
,
T
j
=-40...+150°C
Slew rate on
10 to 30%
V
OUT
,
R
L
= 12
Ω
,
T
j
=-40...+150°C
Slew rate off
70 to 40%
V
OUT
,
R
L
= 12
Ω
,
T
j
=-40...+150°C
Operating Parameters
Operating voltage
5
)
T
j
=-40...+150°C:
Undervoltage shutdown
T
j
=-40...+150°C:
Undervoltage restart
T
j
=-40...+150°C:
Undervoltage restart of charge pump
see diagram page 12
T
j
=-40...+150°C:
Undervoltage hysteresis
∆V
bb(under)
=
V
bb(u rst)
-
V
bb(under)
Overvoltage shutdown
T
j
=-40...+150°C:
Overvoltage restart
T
j
=-40...+150°C:
Overvoltage hysteresis
T
j
=-40...+150°C:
Overvoltage protection
6
)
T
j
=-40°C:
I
bb
=40 mA
T
j
=25...+150°C:
Standby current (pin 3)
T
j
=-40...+25°C
:
V
IN
=0
T
j
=150°C:
Leakage output current (included in
I
bb(off)
)
V
IN
=0
Operating current (Pin 1)
7)
,
V
IN
=5 V
5
)
6)
7
)
--
9
--
30
55
11
--
38
70
--
1
mΩ
A
mA
µs
I
L(ISO)
I
L(GNDhigh)
t
on
t
off
dV /dt
on
-dV/dt
off
50
10
0.4
1
160
--
--
--
300
80
2.5
5
V/µs
V/µs
V
bb(on)
V
bb(under)
V
bb(u rst)
V
bb(ucp)
∆V
bb(under)
V
bb(over)
V
bb(o rst)
∆V
bb(over)
V
bb(AZ)
I
bb(off)
I
L(off)
I
GND
4.5
2.4
--
--
--
42
42
--
60
63
--
--
--
--
--
--
--
6.5
0.2
--
--
0.2
--
67
12
18
6
1.1
42
4.5
4.5
7.5
--
52
--
--
--
25
60
--
--
V
V
V
V
V
V
V
V
V
µA
µA
mA
At supply voltage increase up to
V
bb
= 6.5 V typ without charge pump,
V
OUT
≈V
bb
- 2 V
see also
V
ON(CL)
in table of protection functions and circuit diagram page 7. Meassured without load
.
Add
I
ST
, if
I
ST
> 0, add
I
IN
, if
V
IN
>5.5 V
Semiconductor Group
3
2003-Oct-01
BTS 432 E2
Parameter and Conditions
at T
j
= 25 °C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Protection Functions
8)
Initial peak short circuit current limit (pin 3 to 5)
9
)
,
I
L(SCp)
( max 400
µs
if V
ON
> V
ON(SC)
)
T
j
=-40°C:
T
j
=25°C:
T
j
=+150°C:
Repetitive short circuit current limit
I
L(SCr)
T
j
=
T
jt
(see timing diagrams, page 10)
Short circuit shutdown delay after input pos. slope
T
j
=-40..+150°C:
t
d(SC)
V
ON
>
V
ON(SC)
,
min value valid only, if input "low" time exceeds 30
µs
--
--
24
22
80
--
44
--
35
--
74
--
--
--
400
A
A
µs
V
V
°C
K
J
Output clamp (inductive load switch off)
at V
OUT
= V
bb
- V
ON(CL),
I
L
= 30 mA
Short circuit shutdown detection voltage
(pin 3 to 5)
Thermal overload trip temperature
Thermal hysteresis
Inductive load switch-off energy dissipation
10)
,
T
j Start
= 150 °C, single pulse
V
bb
= 12 V:
V
bb
= 24 V:
Reverse battery (pin 3 to 1)
11
)
Integrated resistor in V
bb
line
Diagnostic Characteristics
Open load detection current
(on-condition)
V
ON(CL)
V
ON(SC)
T
jt
∆
T
jt
E
AS
E
Load12
E
Load24
-V
bb
R
bb
--
--
150
--
--
58
8.3
--
10
--
--
--
--
--
1.7
1.3
1.0
32
--
--
--
--
120
V
Ω
T
j
=-40 °C
:
I
L (OL)
T
j
=25..150°C:
2
2
--
--
900
750
mA
8
)
9
)
10)
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
Short circuit current limit for max. duration of 400
µs,
prior to shutdown (see t
d(SC)
page 4)
While demagnetizing load inductance, dissipated energy in PROFET is
E
AS
=
V
ON(CL)
*
i
L
(t) dt, approx.
V
ON(CL)
2
), see diagram page 8
E
AS
=
1
/
2
*
L
*
I
L
* (
V
ON(CL)
-
V
bb
11
) Reverse load current (through intrinsic drain-source diode) is normally limited by the connected load.
Reverse current I
GND
of
≈
0.3 A at V
bb
= -32 V through the logic heats up the device. Time allowed under
these condition is dependent on the size of the heatsink. Reverse I
GND
can be reduced by an additional
external GND-resistor (150
Ω).
Input and Status currents have to be limited (see max. ratings page 2 and
circuit page 7).
Semiconductor Group
4
2003-Oct-01
BTS 432 E2
Parameter and Conditions
at T
j
= 25 °C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Input and Status Feedback
12
)
Input turn-on threshold voltage
T
j
=-40..+150°C:
Input turn-off threshold voltage
T
j
=-40..+150°C:
Input threshold hysteresis
Off state input current (pin 2)
On state input current (pin 2)
V
IN(T+)
V
IN(T-)
∆
V
IN(T)
V
IN
= 0.4 V:
I
IN(off)
V
IN
= 3.5 V:
I
IN(on)
t
d(ST SC)
t
d(ST)
1.5
1.0
--
1
10
80
350
--
--
0.5
--
25
200
--
2.4
--
--
30
50
400
1600
V
V
V
µA
µA
µs
µs
Status invalid after positive input slope
(short circuit)
T
j=-40 ... +150°C:
Status invalid after positive input slope
(open load)
T
j=-40 ... +150°C:
Status output (open drain)
Zener limit voltage
T
j
=-40...+150°C,
I
ST
= +1.6 mA:
ST low voltage
T
j
=-40...+150°C,
I
ST
= +1.6 mA:
V
ST(high)
V
ST(low)
5.4
--
6.1
--
--
0.4
V
12)
If a ground resistor R
GND
is used, add the voltage drop across this resistor.
Semiconductor Group
5
2003-Oct-01
FPGA/CPLD
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