PROFET® BTS 611 L1
Smart Two Channel Highside Power Switch
Features
•
Overload protection
•
Current limitation
•
Short circuit protection
•
Thermal shutdown
•
Overvoltage protection (including load dump)
•
Fast demagnetization of inductive loads
•
Reverse battery protection
1)
•
Undervoltage and overvoltage shutdown with
auto-restart and hysteresis
•
Open drain diagnostic output
•
Open load detection in ON-state
•
CMOS compatible input
•
Loss of ground and loss of
V
bb
protection
•
Electrostatic discharge
(ESD) protection
Product Summary
Overvoltage protection
Operating voltage
V
bb(AZ)
V
bb(on)
43
5.0 ... 34
both
V
V
channels:
On-state resistance
R
ON
Load current (ISO)
I
L(ISO)
Current limitation
I
L(SCr)
each
parallel
200
100 mΩ
2.3
4.4
A
4
4
A
TO-220AB/7
Application
7
1
1
7
7
• µC
compatible power switch with diagnostic
Standard
feedback for 12 V and 24 V DC grounded loads
•
All types of resistive, inductive and capacitve
loads
•
Replaces electromechanical relays, fuses and discrete circuits
Straight leads
SMD
1
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS
®
technology. Fully protected by embedded protection
functions.
Voltage
source
Overvoltage
protection
Current
limit 1
Gate 1
protection
+ V bb
4
V
Logic
Voltage
sensor
Level shifter
Rectifier 1
Charge
pump 1
Charge
pump 2
Limit for
unclamped
ind. loads 1
Open load
Short to Vbb
detection 1
Current
limit 2
Gate 2
protection
OUT1
3
6
5
Temperature
sensor 1
1
IN1
IN2
ESD
ST
Logic
Level shifter
Rectifier 2
Limit for
unclamped
ind. loads 2
Open load
Short to Vbb
detection 2
OUT2
Temperature
sensor 2
R
O1
GND
R
O2
7
Load
®
PROFET
2
GND
Signal GND
Load GND
1
)
With external current limit (e.g. resistor R
GND
=150
Ω)
in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Semiconductor Group
1
12.96
BTS 611 L1
Pin
1
2
3
4
5
6
7
Symbol
OUT1 (Load, L)
GND
IN1
Vbb
ST
IN2
OUT2 (Load, L)
Function
Output 1, protected high-side power output of channel 1
Logic ground
Input 1, activates channel 1 in case of logical high signal
Positive power supply voltage,
the tab is shorted to this pin
Diagnostic feedback: open drain, low on failure
Input 2, activates channel 2 in case of logical high signal
Output 2, protected high-side power output of channel 2
Maximum Ratings
at
T
j
= 25 °C unless otherwise specified
Parameter
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
T
j Start
=-40 ...+150°C
Load dump protection
2
)
V
LoadDump
=
U
A
+
V
s
,
U
A
= 13.5 V
R
I
3
)
= 2
Ω,
R
L
= 5.3
Ω,
t
d
= 200 ms, IN= low or high
Load current (Short circuit current, see page 5)
Operating temperature range
Storage temperature range
Power dissipation (DC), T
C
≤
25 °C
Inductive load switch-off energy dissipation, single pulse
V
bb
= 12V,
T
j,start
= 150°C,
T
C
= 150°C const.
one channel,
I
L
= 2.3 A, Z
L
= 89 mH, 0
Ω:
both channels parallel,
I
L
= 4.4 A, Z
L
= 47 mH, 0
Ω:
see diagrams on page 9
Symbol
V
bb
V
bb
Values
43
34
60
self-limited
-40 ...+150
-55 ...+150
36
290
580
1.0
2.0
-10 ... +16
±2.0
±5.0
Unit
V
V
V
A
°C
W
mJ
V
Load dump4
)
I
L
T
j
T
stg
P
tot
E
AS
Electrostatic discharge capability (ESD)
(Human Body Model)
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagrams page 7
IN:
V
ESD
all other pins:
kV
V
mA
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
V
IN
I
IN
I
ST
2
)
3)
4)
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins, e.g. with a
150
Ω
resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for the
protection of the input is integrated.
R
I
= internal resistance of the load dump test pulse generator
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Semiconductor Group
2
BTS 611 L1
Thermal Characteristics
Parameter and Conditions
Thermal resistance
Symbol
min
--
--
--
chip - case, both channels:
R
thJC
each channel:
junction - ambient (free air):
R
thJA
SMD version, device on PCB
5)
:
Values
typ
max
--
3.5
--
7.0
--
75
37
Unit
K/W
Electrical Characteristics
Parameter and Conditions,
each channel
at
T
j
= 25 °C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Load Switching Capabilities and Characteristics
On-state resistance (pin 4 to 1 or 7)
I
L
= 1.8 A
T
j
=25 °C:
R
ON
T
j
=150 °C:
each channel
Nominal load current, ISO Norm (pin 4 to 1 or 7)
V
ON
= 0.5 V,
T
C
= 85 °C
each channel:
I
L(ISO)
both channels parallel:
Output current (pin
1
or 7) while GND disconnected
or GND pulled up,
V
bb
=30 V,
V
IN
= 0, see diagram
page 8
Turn-on time
IN
to 90%
V
OUT
:
Turn-off time
IN
to 10%
V
OUT
:
R
L
= 12
Ω
,
T
j
=-40...+150°C
Slew rate on
10 to 30%
V
OUT
,
R
L
= 12
Ω
,
T
j
=-40...+150°C
Slew rate off
70 to 40%
V
OUT
,
R
L
= 12
Ω
,
T
j
=-40...+150°C
--
1.8
3.5
--
160
320
2.3
4.4
--
200
400
--
--
10
mΩ
A
mA
µs
I
L(GNDhigh)
t
on
t
off
dV /dt
on
-dV/dt
off
80
80
0.1
0.1
200
200
--
--
400
400
1
1
V/µs
V/µs
5
)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
Semiconductor Group
3
BTS 611 L1
Parameter and Conditions,
each channel
at
T
j
= 25 °C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Operating Parameters
Operating voltage
6
)
Undervoltage shutdown
Undervoltage restart
T
j
=-40...+150°C:
T
j
=-40...+150°C:
T
j
=-40...+25°C:
T
j
=+150°C:
Undervoltage restart of charge pump
see diagram page 13
Undervoltage hysteresis
∆
V
bb(under)
=
V
bb(u rst)
-
V
bb(under)
Overvoltage shutdown
T
j
=-40...+150°C:
Overvoltage restart
T
j
=-40...+150°C:
Overvoltage hysteresis
T
j
=-40...+150°C:
Overvoltage protection
7
)
T
j
=-40...+150°C:
I
bb
=40 mA
Standby current (pin 4)
V
IN
=0
T
j
=-40...+25°C
:
T
j
= 150°C:
Leakage output current (included in
I
bb(off)
)
V
IN
=0
Operating current (Pin 2)
8)
,
V
IN
=5 V
both channels on,
T
j
=-40...+150°C
Operating current (Pin 2)
8)
one channel on,
T
j
=-40...+150°C:
V
bb(on)
V
bb(under)
V
bb(u rst)
V
bb(ucp)
∆
V
bb(under)
5.0
3.5
--
--
--
34
33
--
42
--
--
--
5.6
0.2
--
--
0.5
47
34
5.0
5.0
7.0
7.0
--
43
--
--
--
V
V
V
V
V
V
V
V
V
V
bb(over)
V
bb(o rst)
∆
V
bb(over)
V
bb(AZ)
I
bb(off)
I
L(off)
I
GND
I
GND
--
--
--
--
--
14
17
--
4
2
30
35
12
6
3
µA
µA
mA
mA
6)
7)
8
)
At supply voltage increase up to
V
bb
= 5.6 V typ without charge pump,
V
OUT
≈
V
bb
- 2 V
See also
V
ON(CL)
in table of protection functions and circuit diagram page 8.
Add
I
ST
, if
I
ST
> 0, add
I
IN
, if
V
IN
>5.5 V
Semiconductor Group
4
BTS 611 L1
Parameter and Conditions,
each channel
at
T
j
= 25 °C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Protection Functions
Initial peak short circuit current limit (pin 4 to 1
or 7)
T
j
=-40°C:
T
j
=25°C:
T
j
=+150°C:
Repetitive short circuit shutdown current limit
T
j
=
T
jt
(see timing diagrams, page 11)
Output clamp (inductive load switch off)
at
V
OUT
=
V
bb
-
V
ON(CL)
I
L
= 40 mA:
Thermal overload trip temperature
Thermal hysteresis
Reverse battery (pin 4 to 2)
9
)
Reverse battery voltage drop
(V
out
> V
bb
)
I
L
= -1.8 A, each channel
T
j
=150 °C:
Diagnostic Characteristics
Open load detection current
(on-condition)
I
L(SCp)
5.5
4.5
2.5
9.5
7.5
4.5
4
47
--
10
--
610
13
11
7
--
53
--
--
32
--
A
I
L(SCr)
--
A
V
°C
K
V
mV
V
ON(CL)
T
jt
∆T
jt
-V
bb
-V
ON(rev)
41
150
--
--
--
T
j
=-40 °C
:
I
L (OL)
T
j
=25 ..150°C:
10
10
2
--
--
3
200
150
4
mA
V
Open load detection voltage
10
) (off-condition)
V
OUT(OL)
T
j
=-40..150°C:
Internal output pull down
(pin 1
or
7 to 2),
V
OUT
=5 V,
T
j
=-40..150°C
R
O
4
10
30
kΩ
9
)
Requires 150
Ω
resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 2 and circuit page 8).
10)
External pull up resistor required for open load detection in off state.
Semiconductor Group
5
FPGA/CPLD
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