FX-702
Low Jitter VCSO Frequency Translator
Previous Part Number FX-730
FX-702
Description
The FX-702 is a low jitter precision frequency translator used to translate input frequencies such as 19.44, 38.88, 77.76 MHz, etc. to
a binary multiple frequency as high as 850 MHz. The FX-702’s superior jitter performance is achieved through the PLL’s integrated
VCSO. The FX-702 is housed in a hermetically sealed leadless surface mount package offered on tape and reel.
Features
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5 x 7.5 x 2.5 mm Package
Frequency Translation up to 850 MHz
VCSO based PLL for Ultra-Low Jitter
CMOS / LVDS / LVPECL Inputs compatible
Differential LVPECL or LVDS Output
CMOS Lock Detect
External Divider for Input Frequencies < 19 MHz
0°/70°C or -40°/+85°C Temperature Range
Fully Compatible for Lead Free Assembly
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Applications
SONET/SDH
10GbE./10.3GbE
Frequency Translation
Clock Smoothing, Clock Switching
FEC Scaling
Block Diagram
VCC
(10)
FIN
(12)
CFIN
(11)
LD
(2)
Phase
Detector
& LD
LFN
(6)
Charge
Pump
CFLN
(7)
VCSO
÷1, ÷4
FOUT
Switch
External
Divider
÷1, ÷4, ÷8,
÷16, ÷32
÷1, ÷2, ÷4
(8)
MODE
(4)
CFOUT
(9)
BRCLK CBRCLK
(4)
(1)
GND
(3, 5, 13)
Figure 1. Functional block diagram
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
1
Rev: 03Apr2009
Performance Specifications
Table 1. Electrical Performance
Parameter
Frequency
1, 2, 3
Input Frequency
Output Frequency
Capture Range (ordering option)
1, 2, 3
Supply
Voltage
2, 3
Current (No Load)
3
LVCMOS Input
2, 3
Input High Voltage
Input Low Voltage
LVPECL Input
Peal-Peak Amplitude Swing
6, 7
Lock Detect Output
Output High Voltage
Logic Low Voltage
Outputs
Mid Level - LVPECL
2, 3
Swing - LVPECL
2, 3
Mid Level - LVDS
2, 3
Swing - LVDS
2, 3
Current
5
Rise Time
4, 5
Fall Time
4, 5
Symmetry
2, 3
Jitter Generation - 622.08MHz output
(12kHz-20MHz BW)
5
(50kHz - 80MHz BW)
5
Operating Temp (ordering option)
1, 3
V
OH
V
OL
Symbol
F
IN
F
OUT
APR
V
CC
I
CC
V
IH
V
IL
2.97
Min
19.44
125
±32, ±50, or ±100
3.3
3.63
100
V
CC
0.8
3.00
Typical
Maximum
850
850
Units
MHz
MHz
ppm
V
mA
V
V
V
V
V
V
mV-pp
V
mV-pp
mA
ps
ps
%
ps-rms
ps-rms
0C
2.0
0
0.20
0.9*V
CC
0.1*V
CC
V
CC
-1.4
450
250
V
CC
-1.25
600
V
CC
-1.2
450
V
CC
-1.0
950
I
OUT
t
R
t
F
SYM
Φ
J
Φ
J
T
OP
45
50
0.21
0.12
0/70, -40/85
20
400
400
55
0.5
0.4
1. See Standard Frequencies and Ordering Information.
2. Parameters are tested with production test circuit below (Fig 1).
3. Parameters are tested at ambient temperature with test limits guard banded for specified operating temperature.
4. Measured from 20% to 80% of a full output swing (Fig 2).
5. Not tested in production, guaranteed by design, verified at qualification.
6. Minimum Input Low Voltage not to exceed 2.125 V. Minimum Input High Voltage not to go below 1.49 V.
7. AC coupling is recommended. There is an internal pull-up and pull-down resistor on all clock inputs (Fin, BRCLK).
Figure 1. LVPECL Test Circuit
Figure 2. 10K LVPECL Waveform
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
2
Rev: 03Apr2009
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied
at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to
absolute maximum ratings for extended periods may adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Input Current
Output Current
Storage Temperature
Soldering Temperature/Duration
Symbol
V
CC
I
IN
I
OUT
T
STR
T
PEAK
/t
P
Ratings
0 to 6
100
25
-55 to 125
260 / 40
Unit
V
mA
mA
0C
0C/sec
Reliability
The FX-702 is capable of meeting the following qualification tests:
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Moisture Sensitivity Level Rating
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
MSL 1
Handling Precautions
Although ESD protection circuitry has been designed into the the FX-702, proper precautions should be taken when handling
and mounting. VI employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD susceptibility testing and
design protection evaluation. ESD thresholds are dependent on the circuit parameters used to define the model.
Table 4. Predicted ESD R$atings
Model
Human Body Model
Charged Device Model
Machine Model
Class
2
C5
M3
Minimum
2000 V
1000 V
200 V
Conditions
MIL-STD 883, Method 3015
JEDEC, JESD22-C101
ESD STM5.2-1999
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
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Rev: 03Apr2009
Table 5. Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
PreHeat Time
Ramp Up
Time Above 217 0C
Time To Peak Temperature
Time At 260 0C
Ramp Down
Symbol
t
S
R
UP
t
L
t
AMB-P
t
P
R
DN
Value
60 sec Min, 180 sec Max
3 0C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
6 0C/sec Max
The device has been qualified to meet the JEDEC
standard for Pb-Free assembly. The temperatures
and time intervals listed are based on the Pb-
Free small body requirements. The temperatures
refer to the topside of the package, measured on
the package body surface. The FX-702 device is
hermetically sealed so an aqueous wash is not an
issue.
Figure 3. Suggested IR Profile
Table 6. Tape and Reel Information
Tape Dimensions (mm)
W
16
F
7.5
Do
1.5
Po
4
P1
8
A
178
B
1.5
Reel Dimensions (mm)
C
13
D
20.2
N
50
W1
16.4
W2
22.4
#/Reel
200
Figure 4. Tape and Reel
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
4
Rev: 03Apr2009
FX702 YWW
CCC-CCCC
▲
XX-XX
Figure 5. Outline Diagram
Table 7. Pin Functions
Pad #
1
2
Symbol
BRCLK
LD
1
I/O
I
O
Level
NC or LVPE-
CL, LVDS
CMOS
Function
NC or
For External divider application = PD Feedback Frequency
Lock Detect
Logic 0 = FX Locked
Logic 1 - No Input
Output transitioning = Out of Lock
Case and electrical ground
FX Operating Mode
Logic 0 = Standard PLL (Normal Setting)
Logic 1 = FIN coupled to FOUT
Case and electrical ground
Loop Filter Node
Complementary Loop Filter Node
Frequency Output
Complementary Frequency Output
Power Supply Voltage (+3.3V ±5%)
Complemetary Input Frequency
For CMOS inouts, AC-couple unused inputto ground or negative supply
Input Frequency
Case and electrical ground
NC or
For External divider applications = Comp. PD Feedback Frequency
3
4
GND
MODE
2
GND
I
Supply
CMOS
5
6
7
8
9
10
11
12
13
14
1.
2.
3.
4.
GND
LFN
CLFN
FOUT
CFOUT
VCC
CFIN
FIN
GND
CBRCLK
GND
Supply
Analog
Analog
O
O
I
I
I
GND
I
LVPECL or
LVDS
LVPECL or
LVDS
Supply
LVPECL
CMOS or
LVPECL
Supply
NC or LVPE-
CL, LVDS
It is recommended that a buffer driver is used for best noise isolation.
Do not leave the MODE pin floating, it should be set to logic 0 or ground for normal operation.
BRCLK and CBRCLK should be left floating if not used.
FIN, CFIN, BRCLK, and CBRCLK have internal pull-up/pull-down resistors and it is recommended to AC couple these inputs.
5 of 7
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
5
Rev: 03Apr2009
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