K9K1208U0A-YCB0, K9K1208U0A-YIB0
Document Title
64M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.0
FLASH MEMORY
History
1. Initial issue
- Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection).
So, /SE pin is don’
t-cared regardless of external logic input level and is
fixed as low internally.
Draft Date
Dec. 6th 2000
Remark
Preliminary
0.1
1. Changed plane address in Copy-Back Program
Dec. 28th 2000
-
A14,
the plane address, of source and destination page address must be
the same. =>
A14 and A25,
the plane address, of source and destination
page address must be the same.
1. In addition, explain WE function in pin description
- The WE must be held high when outputs are activated.
Jan. 17th 2001
Final
0.2
Note : For more detailed features and specifications including FAQ, please refer to Samsung’ Flash web site.
s
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
64M x 8 Bit NAND Flash Memory
FEATURES
•
Voltage Supply : 2.7V~3.6V
•
Organization
- Memory Cell Array : (64M + 2,048K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
•
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
•
528-Byte Page Read Operation
- Random Access : 10µs(Max.)
- Serial Page Access : 60ns(Min.)
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Package :
- K9K1208U0A-YCB0/YIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
The K9K1208U0A are a 64M(67,108,864)x8bit NAND Flash
Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation programs the 528-
byte page in typically 200µs and an erase operation can be per-
formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 60ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. Even the
write-intensive systems can take advantage of the
K9K1208U0A′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. The K9K1208U0A-YCB0/YIB0 is an
optimum solution for large nonvolatile storage applications such
as solid state file storage and other portable applications requir-
ing non-volatility.
PIN CONFIGURATION
PIN DESCRIPTION
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Pin Name
I/O
0
~ I/O
7
CLE
ALE
CE
RE
WE
WP
R/B
V
CC
V
SS
N.C
Pin Function
Data Input/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready/Busy output
Power
Ground
No Connection
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
2
K9K1208U0A-YCB0, K9K1208U0A-YIB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
V
CC
V
SS
A
9
- A
25
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
FLASH MEMORY
512M + 16M Bit
NAND Flash
ARRAY
A
0
- A
7
(512 + 16)Byte x 131072
Page Register & S/A
A
8
Command
Command
Register
Y-Gating
I/O Buffers & Latches
V
CC
V
SS
I/0 0
I/0 7
CE
RE
WE
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block = 32 Pages
= (16K + 512) Byte
128K Pages
(=4,096 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
1 Page = 528 Byte
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 4,096 Blocks
= 528 Mbits
8 bit
16 Byte
512B Byte
Page Register
512 Byte
16 Byte
I/O 0 ~ I/O 7
I/O 0
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A
0
A
9
A
17
A
25
I/O 1
A
1
A
10
A
18
*L
I/O 2
A
2
A
11
A
19
*L
I/O 3
A
3
A
12
A
20
*L
I/O 4
A
4
A
13
A
21
*L
I/O 5
A
5
A
14
A
22
*L
I/O 6
A
6
A
15
A
23
*L
I/O 7
A
7
A
16
A
24
*L
Column Address
Row Address
(Page Address)
NOTE
: Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A
8
is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
3
K9K1208U0A-YCB0, K9K1208U0A-YIB0
PRODUCT INTRODUCTION
FLASH MEMORY
The K9K1208U0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1208U0A.
The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address
cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9K1208U0A.
Table 1. COMMAND SETS
Function
Read 1
Read 2
Read ID
Reset
Page Program
Block Erase
Read Status
1st. Cycle
00h/01h
(1)
50h
90h
FFh
80h
60h
70h
2nd. Cycle
-
-
-
-
10h
D0h
-
O
O
Acceptable Command during Busy
NOTE
: 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half
register(00h) on the next cycle.
4
K9K1208U0A-YCB0, K9K1208U0A-YIB0
PIN DESCRIPTION
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
REA
after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
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