PRELIMINARY
MAY 2006
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Offered in both 16 pin SOIC and TSSOP packages,
XRK32309 is a low cost 3.3V zero delay buffer. It is
designed to distribute high speed clocks by taking
one reference input and driving nine output clocks.
The feedback of its on-chip PLL is internally
connected to the FB output. XRK32309 devices
operate over 10-100 MHz frequency range with 30 pF
loads and up to 120MHz with lower loads (10 pF).
The -1H version has higher drive strength than the
base -1 version, featuring faster rise and fall time.
The XRK32309 has two banks each with four
outputs. These outputs are controlled by two select
input lines according to the Table 2, “Select Input
Decoding,” on page 3. In cases where not all outputs
are needed, bank B can be tri-stated. The select
lines also enable putting the device in a bypass mode
where the input is directly applied to the outputs. This
feature is useful for chip and testing purposes.
Some applications may require distributing the clock
to several destinations. In such situations, multiple
XRK32309 devices can be connected to accept the
same input clock and generate several clock signals.
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRK32309
In this case, the skew between the outputs of two
devices is guaranteed to be less than 700 ps.
The available versions of XRK32309 are shown in
Table 12, “Ordering Information,” on page 10. The
XRK32309-1 is the base part.
FEATURES
•
10-MHz to 120-MHz operating range, compatible
with CPU and PCI bus frequencies
•
Zero input-output propagation delay
•
Multiple low-skew outputs
■
■
■
Output-output skew less than 250 ps
Device-device skew less than 700 ps
One input drives nine outputs, grouped as 4 +
4+1
•
Less than 200 ps cycle-cycle jitter, compatible with
Pentium -based systems
•
Test Mode to bypass phase-locked loop (PLL) (see
“Select Input Decoding” on page 2)
•
Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages
•
3.3V operation
•
Industrial and commercial temperature available
PLL
REF
MUX
QA0
QA1
QA2
QA3
S2
S1
Select Input
Decoding
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
®
FB
QB0
QB1
QB2
QB3
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
F
IGURE
2. P
IN
O
UT OF THE
XRK32309
PRELIMINARY
REV. P1.0.1
16 SOIC/TSSOP
REF
QA0
QA1
V
DD
GND
QB0
QB1
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB
QA3
QA2
V
DD
GND
QB3
QB2
S1
T
ABLE
1: P
IN
D
ESCRIPTION FOR
XRK32309
P
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[1]
QA0
[2]
QA1
[2]
V
DD
GND
QB0
[2]
QB1
[2]
S2
[3]
S1
[3]
QB2
[2]
QB3
[2]
GND
V
DD
QA2
[2]
QA3
[2]
FB
[2]
S
IGNAL
Input reference frequency.
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
D
ESCRIPTION
2
PRELIMINARY
REV. P1.0.1
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
T
ABLE
2: S
ELECT
I
NPUT
D
ECODING
S2
0
0
1
1
N
OTES
:
1.
2.
3.
4.
S1
0
1
0
1
QA0-QA3
Tri-Stated
Driven
Driven
Driven
QB0-QB3
Tri-Stated
Tri-Stated
Driven
Driven
FB
[4]
Driven
Driven
Driven
Driven
O
UTPUT
S
OURCE
PLL
PLL
Reference
PLL
Weak pull-down.
Weak pull-down on all outputs.
Weak pull-ups on these inputs.
This output has an internal feedback for the PLL. The load on this output can be adjusted to change the skew
between the reference and output.
F
IGURE
3. REF. I
NPUT TO
QA
X
/QB
X
D
ELAY VS
. L
OADING
D
IFFERENCE BETWEEN
FB
AND
QA
X
/QB
X
P
INS
1500
1000
REF Input to QAx/QBx Delay (ps)
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FB Load - QAx/QBx Load (pF)
Note: Target only, actual characterization curve may be slightly different.
ZERO DELAY AND SKEW CONTROL
In order to achieve Zero Delay between the input reference and the output, all outputs, including FB, must be
equally loaded even when the FB output is not being used.
Being internally connected as the PLL feedback, the FB output's capacitive loading relative to the other
outputs can adjust the input to output delay according to the characteristic shown in Figure 3. This figure
provides a tool for mapping the required delay to the capacitive load difference required between the FB and
the Clock output of interest.
For zero output to output skew, the outputs have to be loaded equally as well.
3
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
PRELIMINARY
REV. P1.0.1
T
ABLE
3: A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage REF
Storage Temperature
Junction Temperature
Static Discharge Voltage (per MIL-STD-883, Method 3015)
R
ANGE
-0.5V to +7.0V
-0.5V to V
DD
+0.5V
-0.5 to 7V
-65°C to +150°C
150°C
>2000V
T
ABLE
4: O
PERATING
C
ONDITIONS FOR
XRK32309SC-XX C
OMMERCIAL
T
EMPERATURE
D
EVICES
P
ARAMETER
V
DD
T
A
C
L
Load Capacitance, from 100MHz to 120MHz
C
IN
t
PU
Input Capacitance
Power-up time for all V
DD
’s to reach minimum
specified voltage (power ramps must be monotonic)
-
-
0.05
10
7
50
pF
pF
ms
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100MHz
D
ESCRIPTION
M
IN
3.0
0
-
M
AX
3.6
70
30
U
NIT
V
°C
pF
T
ABLE
5: E
LECTRICAL
C
HARACTERISTICS FOR
XRK32309SC-XX C
OMMERCIAL
T
EMPERATURE
D
EVICES
P
ARAMETER
V
IL
V
IH
I
IL
I
IH
V
OL
D
ESCRIPTION
Input Low Voltage
[5]
Input High Voltage
[5]
Input Low Current
Input High Current
Output Low Voltage
[6]
V
IN
=0V
V
IN
=V
DD
I
OL
= 8mA (-1)
I
OL
= 12mA (-1H)
V
OH
Output High Voltage
[6]
I
OH
= -8mA (-1)
I
OH
= -12mA (-1H)
I
DD
Supply Current
Unloaded outputs at 66.67MHz,
SEL inputs at V
DD
-
32.0
mA
2.4
-
V
T
EST
C
ONDITIONS
M
IN
-
2.0
-
-
-
M
AX
0.8
-
50.0
100.0
0.4
U
NIT
V
V
µA
µA
V
4
PRELIMINARY
REV. P1.0.1
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
T
ABLE
6: S
WITCHING
C
HARACTERISTICS FOR
XRK32309SC-1 C
OMMERCIAL
T
EMPERATURE
D
EVICES[7]
P
ARAMETER
t
1
DC
t
3
t
4
t
5
t
6A
N
AME
Output Frequency
30-pF load
10-pF load
Measured at 1.4V, F
OUT
=66.67MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
T
EST
C
ONDITIONS
M
IN
10
10
40.0
-
-
-
-
T
YP
-
M
AX
100
120
60.0
2.50
2.50
250
±350
U
NIT
MHz
MHz
%
ns
ns
ps
ps
Duty Cycle
[6]
= t
2
÷
t
1
Rise Time
[6]
Fall Time
[6]
Output to Output Skew
[6]
50.0
-
-
-
0
Delay, REF Rising Edge to Measured at V
DD
/2
FB Rising Edge
[6]
Delay, REF Rising Edge to Measured at V
DD
/2. Measured in PLL
Bypass Mode
FB Rising Edge
[6]
Device to Device Skew
[6]
Cycle to Cycle Jitter
[6]
PLL Lock Time
[6]
Measured at V
DD
/2 on the FB pins of
devices
Measured at 66.67MHz, loaded outputs
Stable power suppy, valid clock
presented on REF pin
t
6B
1
5
8.7
ns
t
7
t
J
t
LOCK
-
0
700
ps
-
-
-
-
200
1.0
ps
ms
N
OTES
:
5.
6.
7.
REF input has a threshold voltage of V
DD
/2.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
All parameters specified with loaded outputs.
5
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