CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
72-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
Features
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Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1566KV18 – 8 M × 8
CY7C1577KV18 – 8 M × 9
CY7C1568KV18 – 4 M × 18
CY7C1570KV18 – 2 M × 36
72-Mbit density (8 M × 8, 8 M × 9, 4 M × 18, 2 M × 36)
550 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
1100 MHz) at 550 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
DDR II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
Core V
DD
= 1.8 V ± 0.1 V; I/O V
DDQ
= 1.4 V to V
DD[1]
❐
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Functional Description
The CY7C1566KV18, CY7C1577KV18, CY7C1568KV18, and
CY7C1570KV18 are 1.8 V Synchronous Pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1566KV18), 9-bit words (CY7C1577KV18), 18-bit
words (CY7C1568KV18), or 36-bit words (CY7C1570KV18) that
burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4 V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-15880 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 25, 2011
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CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
Contents
Selection Guide ................................................................ 5
Pin Configuration ............................................................. 6
165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 6
Pin Definitions .................................................................. 8
Functional Overview ...................................................... 10
Read Operations ....................................................... 10
Write Operations ....................................................... 10
Byte Write Operations ............................................... 10
DDR Operation .......................................................... 10
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
Valid Data Indicator (QVLD) ...................................... 11
PLL ............................................................................ 11
Application Example ...................................................... 11
Truth Table ...................................................................... 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 13
Write Cycle Descriptions ............................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port—Test Clock ................................... 14
Test Mode Select (TMS) ........................................... 14
Test Data-In (TDI) ..................................................... 14
Test Data-Out (TDO) ................................................. 14
Performing a TAP Reset ........................................... 14
TAP Registers ........................................................... 14
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 16
TAP Controller Block Diagram ...................................... 17
TAP Electrical Characteristics ...................................... 17
TAP AC Switching Characteristics ............................... 18
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in DDR II+ SRAM ......................... 21
Power Up Sequence ................................................. 21
PLL Constraints ......................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Neutron Soft Error Immunity ......................................... 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 24
Thermal Resistance ........................................................ 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 26
Read/Write/Deselect Sequence ................................ 26
Ordering Code Definitions ......................................... 27
Ordering Information ...................................................... 27
Package Diagram ............................................................ 28
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC Solutions ......................................................... 31
Document Number: 001-15880 Rev. *K
Page 4 of 31
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