• Application compatibility for a wide variety of designs
• Enables design compatibility
• Lower drive strength settings (CY241V08A–06)
Benefits
• Digital VCXO control
• Electromagnetic interference (EMI) reduction for standards
compliance
• Second source for existing designs
• Highest-performance PLL tailored for multimedia applica-
tions
• Meets critical timing requirements in complex system
designs
CY241V08A–05,–06 Logic Block Diagram
13.5 XIN
XOUT
OSC
Q
Φ
VCO
P
OUTPUT
DIVIDERS
27 MHz
VCXO
PLL
VDD
VSS
Pin Configurations
CY241V08A–05,–06
8-pin SOIC
XIN
VDD
VCXO
VSS
1
2
3
4
8
7
6
5
XOUT
NC or VSS
NC or VDD
27 MHz
Part
Number
CY241V08A–05
Outputs
1
Input Frequency Range
Output
Frequencies
VCXO Control
Curve
Other Features
Compatible with
MK3727A non linear
VCXO control
Same as CY241V08A–05
except lower drive
strength
13.5-MHz pullable crystal input per 1 copy of 27 MHz non-linear
Cypress specification
13.5-MHz pullable crystal input per 1 copy of 27 MHz non-linear
Cypress specification
CY241V08A–06
1
Cypress Semiconductor Corporation
Document #: 38-07670 Rev. **
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 09, 2004
CY241V08A-05,06
Pin Description
Name
XIN
VDD
VCXO
VSS
27 MHz
NC/VDD
NC/VSS
XOUT
Pin Number
1
2
3
4
5
6
7
8
Reference crystal input
Voltage supply
Input analog control for VCXO
Ground
27-MHz clock output
No connect or voltage supply
No connect or ground
Reference crystal output
Description
Document #: 38-07670 Rev. **
Page 2 of 6
CY241V08A-05,06
Absolute Maximum Conditions
Supply Voltage (V
DD
) ........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing)..... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883................. > 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Pullable Crystal Specifications
[1]
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
Description
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR) Fundamental mode
Ratio of third overtone mode ESR Ratio used because typical R
1
values
to fundamental mode ESR
are much less than the maximum spec
Crystal drive level
Third overtone separation from
3*F
NOM
Third overtone separation from
3*F
NOM
Crystal shunt capacitance
Ratio of shunt to motional capaci-
tance
Crystal motional capacitance
No external series resistor assumed
High side
Low side
Comments
Parallel resonance, fundamental mode,
AT cut
Min.
–
–
–
3
150
300
–
–
180
14.4
Typ.
13.5
14
–
–
–
–
–
–
–
18
Max.
–
–
25
–
–
–
–150
7
250
21.6
Unit
MHz
pF
Ω
–
µW
ppm
ppm
pF
–
fF
Recommended Operating Conditions
Parameter
VDD
T
A
C
LOAD
t
PU
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power-up time for all VDD pins to reach minimum specified voltage
(power ramps must be monotonic)
Description
Min.
3.135
0
–
0.05
Typ.
3.3
–
–
–
Max.
3.465
70
15
500
Unit
V
°C
pF
ms
DC Electrical Specifications
Parameter
I
OH
I
OL
C
IN
V
VCXO
f
∆XO
[2]
Name
Output HIGH Current
Output LOW Current
Input Capacitance
VCXO Input Range
VCXO Pullability Range
Supply Current
Low Side
Description
V
OH
= V
DD
– 0.5V, V
DD
= 3.3V
V
OL
= 0.5V, V
DD
= 3.3V
Except XIN, XOUT pins
Min.
12
12
–
0
–
75
–
Typ.
24
24
–
–
–
–
30
Max.
–
–
7
V
DD
–75
–
35
Unit
mA
mA
pF
V
ppm
ppm
mA
High Side
I
VDD
Notes:
1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC.
2. –75/+75 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less
board capacitance.
Document #: 38-07670 Rev. **
Page 3 of 6
CY241V08A-05,06
AC Electrical Specifications
(V
DD
= 3.3V)
[3]
Parameter
[3]
DC
ER
OR
ER
OF
ER
OR
ER
OF
t
9
t
10
Name
Output Duty Cycle
Rising Edge Rate –05
Falling Edge Rate –05
Rising Edge Rate –06
Falling Edge Rate –06
Clock Jitter
PLL Lock Time
Description
Duty Cycle is defined in
Figure 1,
50% of V
DD
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF See
Figure 2.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See
Figure 2.
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF See
Figure 2.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See
Figure 2.
Peak-to-peak period jitter
Min.
45
0.8
0.8
0.7
0.7
–
–
Typ.
50
1.4
1.4
1.1
1.1
–
–
Max.
55
–
–
–
–
100
3
Unit
%
V/ns
V/ns
V/ns
V/ns
ps
ms
Test and Measurement Set-up
VDD
0.1
µF
DUT
Outputs
C
LOAD
GND
Voltage and Timing Definitions
t
1
t
2
V
DD
50% of V
DD
Clock
Output
0V
Figure 1. Duty Cycle Definition
t
3
t
4
V
DD
80% of V
DD
Clock
Output
20% of V
DD
0V
Figure 2. ER = (0.6 x V
DD
) /t3, EF = (0.6 x V
DD
) /t4
Note:
3. Not 100% tested.
Document #: 38-07670 Rev. **
Page 4 of 6
CY241V08A-05,06
Ordering Information
Ordering Code
CY241V08ASC–05,06
CY241V08ASC–05,06T
Package
Name
S8
S8
Package Type
8-pin SOIC
Operating
Range
Commercial
Operating
Voltage
3.3V
3.3V
Features
Linear VCXO control curve
Linear VCXO control curve
8-pin SOIC - Tape and Reel Commercial
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
0.150[3.810]
0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
SEATING PLANE
0.010[0.254]
0.016[0.406]
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
All product or company names mentioned in this document may be the trademarks of their respective holders.
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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