on design changes and product performance enhancements, and better
inventory control. Parts can be reprogrammed up to 100 times, reducing
inventory of custom parts and providing an easy method for upgrading
existing designs.
In-house programming of samples and prototype quantities is available
using the CY3672 FTG Development Kit. Production quantities are
available through Cypress’s value-added distribution partners or by using
third party programmers from BP Microsystems, HiLo Systems, and
others.
High performance suited for commercial, industrial, networking, telecomm
and other general-purpose applications.
Application compatibility in standard and low-power systems.
Industry standard packaging saves on board space.
Input Frequency Range
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
Output Frequency Range
80 kHz–200 MHz (3.3V)
80 KHz–166.6 MHz (2.5V)
80 kHz–166.6 MHz (3.3V)
80 KHz–150 MHz (2.5V)
Specifications
Field-programmable
commercial temperature
Field-programmable
industrial temperature
LCLK1
Divider
Bank 1
Output
Select
Matrix
VCO
P
PLL
Divider
Bank 2
CLK5
CLK6
LCLK2
LCLK3
LCLK4
• Field-programmable
• Low-skew, low-jitter, high-accuracy outputs
• 3.3V operation with 2.5V output option
• 16-lead TSSOP
Part Number
CY22050FC
CY22050FI
Outputs
6
6
Logic Block Diagram
XIN
XOUT
OSC.
Q
Φ
OE
VDD
AVDD AVSS
VSS
VDDL
VSSL
PWRDWN
Pin Configuration
XIN
VDD
AVDD
PWRDWN
AVSS
VSSL
LCLK1
LCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
CLK6
CLK5
VSS
LCLK4
VDDL
OE
LCLK3
Cypress Semiconductor Corporation
Document #: 38-07006 Rev. *D
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 29, 2005
CY22050
CY22050 Pin Summary
Name
XIN
Pin Number
1
Description
Reference Input.
Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based
on manufacturer, process, performance, or quality.
3.3V voltage supply
3.3V analog voltage supply
Power Down.
When pin 4 is driven LOW, the CY22050 will go into shut-down mode.
Analog ground
LCLK ground
Configurable clock output 1 at V
DDL
level (3.3V or 2.5V)
Configurable clock output 2 at V
DDL
level (3.3V or 2.5V)
Configurable clock output 3 at V
DDL
level (3.3V or 2.5V)
Output Enable.
When pin 10 is driven LOW, all outputs are three-stated.
LCLK voltage supply (2.5V or 3.3V)
Configurable clock output 4 at V
DDL
level (3.3V or 2.5V)
Ground
Configurable clock output 5 (3.3V)
Configurable clock output 6 (3.3V)
Reference output
outputs an industry-standard
programming the CY22050.
JEDEC
file
used
for
VDD
AVDD
PWRDWN
[1]
AVSS
VSSL
LCLK1
LCLK2
LCLK3
OE
[1]
VDDL
LCLK4
VSS
CLK5
CLK6
XOUT
[2]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Functional Description
The CY22050 is the next-generation programmable FTG
(frequency timing generator) for use in networking, telecom-
munication, datacom, and other general-purpose applications.
The CY22050 offers up to six configurable outputs in a 16-pin
TSSOP, running off a 3.3V power supply. The on-chip
reference oscillator is designed to run off an 8–30-MHz crystal,
or a 1–133-MHz external clock signal.
The CY22050 has a single PLL driving 6 programmable output
clocks. The output clocks are derived from the PLL or the
reference frequency (REF). Output post dividers are available
for either. Four of the outputs can be set as 3.3V or 2.5V, for
use in a wide variety of portable and low-power applications.
Field Programming the CY22050F
The CY22050 is programmed at the package level, i.e., in a
programmer socket. The CY22050 is flash-technology based,
so the parts can be reprogrammed up to 100 times. This allows
for fast and easy design changes and product updates, and
eliminates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distri-
bution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large-production quantities.
CyClocksRT Software
CyClocksRT™ is an easy-to-use software application that
allows the user to custom-configure the CY22050. Users can
specify the REF, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyClocksRT
CyClocksRT can be downloaded free of charge from the
Cypress website at http://www.cypress.com.
CY3672 FTG Development Kit
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY22050 and
program samples and small prototype quantities. The kit
comes with the latest version of CyClocksRT and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyClocksRT can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise,
long-term jitter, cycle-to-cycle jitter, period jitter, absolute jitter,
and deterministic jitter. These jitter terms are usually given in
terms of rms, peak-to-peak, or in the case of phase noise
dBC/Hz with respect to the fundamental frequency. Actual
jitter is dependent on XIN jitter and edge rate, number of active
outputs, output frequencies, V
DDL
(2.5V or 3.3V), temperature,
and output load.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-µF ceramic
cap) of the clock and ensuring a low-impedance ground to the
Notes:
1. The CY22050 has no internal pull-up or pull-down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground.
2. Float XOUT if XIN is driven by an external clock source.
Document #: 38-07006 Rev. *D
Page 2 of 9
CY22050
chip. Reducing capacitive clock output loading to a minimum
lowers current spikes on the clock edges and thus reduces
jitter.
Reducing the total number of active outputs will also reduce
jitter in a linear fashion. However, it is better to use two outputs
to drive two loads than one output to drive two loads.
The rate and magnitude that the PLL corrects the VCO
frequency is directly related to jitter performance. If the rate is
too slow, then long term jitter and phase noise will be poor.
Therefore, to improve long-term jitter and phase noise,
reducing Q to a minimum is advisable. This technique will
increase the speed of the phase frequency detector, which in
turn drives the input voltage of the VCO. In a similar manner,
increasing P until the VCO is near its maximum rated speed
will also decrease long term jitter and phase noise. For
example: input reference of 12 MHz; desired output frequency
of 33.3 MHz. One might arrive at the following solution: Set
Q = 3, P = 25, Post Div = 3. However, the best jitter results will
be Q = 2, P = 50, Post Div = 9.
For additional information, refer to the application note, “Jitter
in PLL-based Systems: Causes, Effects, and Solutions,”
available at http://www.cypress.com (click on “Application
Notes”), or contact your local Cypress Field Applications
Engineer.
There are four variables used to determine the final output
frequency. They are: the input REF, the P and Q dividers, and
the post divider. The three basic formulas for determining the
final output frequency of a CY22150-based design are:
• CLK = ((REF * P)/Q)/Post Divider
• CLK = REF/Post Divider
• CLK = REF
The basic PLL block diagram is shown in
Figure 1.
Each of the
six clock outputs has a total of seven output options available
to it. There are six post divider options: /2 (two of these), /3, /4,
/DIV1N, and DIV2N. DIV1N and DIV2N are separately calcu-
lated and can be independent of each other. The post divider
options can be applied to the calculated PLL frequency or to
the REF directly.
In addition to the six post divider options, the seventh option
bypasses the PLL and passes the REF directly to the cross-
point switch matrix.
Clock Output Settings: Crosspoint Switch
Matrix
Each of the six clock outputs can come from any of seven
unique frequency sources. The crosspoint switch matrix
defines which source is attached to each individual clock
output. Although it may seem that there are an unlimited
number of divider options, there are several rules that should
be taken into account when selecting divider options.
Divider Bank 1
CY22050 Frequency Calculation
The CY22050 is an extremely flexible clock generator with up
to six individual outputs, generated from an integrated PLL.
/DIV1N
LCLK1
LCLK2
LCLK3
Crosspoint
Switch
Matrix
REF
Q
PFD
P
VCO
/2
/
3
Divider Bank 2
LCLK4
CLK5
CLK6
/
4
/
2
/DIV2N
Figure 1. Basic PLL Block Diagram
Clock Output Divider
None
/DIV1N
/2
/3
/DIV2N
/2
/4
Definition and Notes
Clock output source is the reference input frequency
Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are
4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible
by 4.
Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6.
Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are
4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible
by 4.
Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be
divisible by 8.
Page 3 of 9
Document #: 38-07006 Rev. *D
CY22050
Reference Crystal Input
The input crystal oscillator of the CY22050 is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference clock source. The oscillator inverter
has programmable gain, allowing for maximum compatibility
with a reference crystal, based on manufacturer, process,
performance, and quality.
The value of the input load capacitors is determined by eight
bits in a programmable register. Total load capacitance is
determined by the formula:
CapLoad = (C
L
– C
BRD
– C
CHIP
)/0.09375 pF
In CyClocksRT, enter the crystal capacitance (C
L
). The value
of CapLoad will be determined automatically and programmed
into the CY22050.
If you require greater control over the CapLoad value, consider
using the CY22150F for serial configuration and control of the
input load capacitors. For an external clock source, the default
is 0.
Input load capacitors are placed on the CY22050 die to reduce
external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency
shift that occurs when non-linear load capacitance is affected
by load, bias, supply, and temperature changes.
Absolute Maximum Conditions
Parameter
V
DD
V
DDL
T
S
T
J
Supply Voltage
I/O Supply Voltage
Storage Temperature
[3]
Junction Temperature
Package Power Dissipation—Commercial Temp
Package Power Dissipation—Industrial Temp
Digital Inputs
Digital Outputs referred to V
DD
Digital Outputs referred to V
DDL
ESD
Static Discharge Voltage per MIL-STD-833, Method 3015
AV
SS
– 0.3
V
SS
– 0.3
V
SS
– 0.3
Description
Min.
–0.5
–0.5
–65
Max.
7.0
7.0
125
125
450
380
AV
DD
+ 0.3
V
DD
+ 0.3
V
DDL
+0.3
2000
Unit
V
V
°C
°C
mW
mW
V
V
V
V
Recommended Operating Conditions
Parameter
V
DD
VDDL
HI
VDDL
LO
T
AC
T
AI
C
LOAD
C
LOAD
f
REFD
f
REFC
t
PU
Description
Operating Voltage
Operating Voltage
Operating Voltage
Ambient Commercial Temp
Ambient Industrial Temp
Max. Load Capacitance V
DD
/V
DDL
= 3.3V
Max. Load Capacitance V
DDL
= 2.5V
Driven REF
Crystal REF
Power-up time for all V
DD
s to reach minimum
specified voltage (power ramps must be
monotonic)
1
8
0.05
Min.
3.135
3.135
2.375
0
–40
Typ.
3.3
3.3
2.5
Max.
3.465
3.465
2.625
70
85
15
15
133
30
500
Unit
V
V
V
°C
°C
pF
pF
MHz
MHz
ms
Note:
3. Rated for 10 years.
Document #: 38-07006 Rev. *D
Page 4 of 9
CY22050
DC Electrical Characteristics
Parameter
[4]
I
OH3.3
I
OL3.3
I
OH2.5
I
OL2.5
V
IH
V
IL
I
VDD[5,6]
I
VDDL3.3[5,6]
I
VDDL2.5[5,6]
I
DDS
I
OHZ
I
OLZ
Name
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Supply Current
Supply Current
Supply Current
Power-Down Current
Output Leakage
Description
V
OH
= V
DD
– 0.5V, V
DD
/V
DDL
= 3.3V
V
OL
= 0.5V, V
DD
/V
DDL
= 3.3V
V
OH
= V
DDL
– 0.5V, V
DDL
= 2.5V
V
OL
= 0.5V, V
DDL
= 2.5V
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
AV
DD
/V
DD
Current
V
DDL
Current (V
DDL
= 3.465V)
V
DDL
Current (V
DDL
= 2.625V)
V
DD
= V
DDL
= AV
DD
= 3.465V
V
DD
= V
DDL
= AV
DD
= 3.465V
Min.
12
12
8
8
0.7
0
45
25
17
50
10
Typ.
24
24
16
16
1.0
0.3
Max.
Unit
mA
mA
mA
mA
V
DD
V
DD
mA
mA
mA
µA
µA
AC Electrical Characteristics
Parameter
[4]
t1
Name
Output frequency,
commercial temp
Output frequency,
industrial temp
t2
Output duty cycle
Description
Clock output limit, 3.3V
Clock output limit, 2.5V
Clock output limit, 3.3V
Clock output limit, 2.5V
Duty cycle is defined in
Figure 2;
t1/t2
f
OUT
> 166 MHz, 50% of V
DD
Duty cycle is defined in
Figure 2;
t1/t2
f
OUT
< 166 MHz, 50% of V
DD
t3
LO
t4
LO
t3
HI
t4
HI
t5
[7]
t6
[8]
t10
Rising edge slew
rate (V
DDL
= 2.5V)
Falling edge slew
rate (V
DDL
= 2.5V)
Rising edge slew
rate (V
DDL
= 3.3V)
Falling edge slew
rate (V
DDL
= 3.3V)
Skew
Clock jitter
PLL lock time
Output clock rise time, 20% – 80% of V
DDL
.
Defined in
Figure 3
Output clock fall time, 80% – 20% of V
DDL
.
Defined in
Figure 3
Output clock rise time, 20% – 80% of
V
DD
/V
DDL
. Defined in
Figure 3
Output clock fall time, 80% – 20% of
V
DD
/V
DDL
. Defined in
Figure 3
Output-output skew between related outputs
Peak-to-peak period jitter (see
Figure 4)
250
0.30
3
Min.
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
40
45
0.6
0.6
0.8
0.8
50
50
1.2
1.2
1.4
1.4
250
Typ.
Max.
200
166.6
166.6
150
60
55
Unit
MHz
MHz
MHz
MHz
%
%
V/ns
V/ns
V/ns
V/ns
ps
ps
ms
Notes:
4. Not 100% tested, guaranteed by design.
5. I
VDD
currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz.
6. Use CyClocksRT to calculate actual I
VDD
and I
VDDL
for specific output frequency configurations.
7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information.
8. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, V
DDL
(2.5V or 3.3V), temperature,
and output load. For more information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cy-
press.com, or contact your local Cypress Field Applications Engineer.
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