CY14C512Q
CY14B512Q
CY14E512Q
512-Kbit (64K × 8) SPI nvSRAM
512-Kbit (64K × 8) SPI nvSRAM
Features
■
■
512-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 64K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
❐
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐
Support automatic STORE on power-down with a small
capacitor (except for CY14X512Q1A)
Industry standard configurations
❐
Operating voltages:
• CY14C512Q: V
CC
= 2.4 V to 2.6 V
• CY14B512Q: V
CC
= 2.7 V to 3.6 V
• CY14E512Q: V
CC
= 4.5 V to 5.5 V
❐
Industrial temperature
❐
8- and 16-pin small outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14X512Q combines a 512-Kbit nvSRAM
[1]
with
a nonvolatile element in each memory cell with serial SPI
interface. The memory is organized as 64 K words of 8 bits each.
The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place automati-
cally at power-down (except for CY14X512Q1A). On power-up,
data is restored to the SRAM from the nonvolatile memory
(RECALL operation). You can also initiate the STORE and
RECALL operations through SPI instruction
For a complete list of related documentation, click
here.
High reliability
❐
Infinite read, write, and RECALL cycles
❐
1million STORE cycles to QuantumTrap
❐
Data retention: 20 years at 85
C
■
40-MHz, and 104-MHz High-speed serial peripheral interface
(SPI)
❐
40-MHz clock rate SPI write and read with zero cycle delay
❐
104-MHz clock rate SPI write and SPI read (with special fast
read instructions)
❐
Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■
■
SPI access to special functions
❐
Nonvolatile STORE/RECALL
❐
8-byte serial number
❐
Manufacturer ID and Product ID
❐
Sleep mode
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software protection using Write Disable instruction
❐
Software block protection for 1/4, 1/2, or entire array
Low power consumption
❐
Average active current of 3 mA at 40 MHz operation
❐
Average standby mode current of 150
A
❐
Sleep mode current of 8
A
V
CC
V
CAP
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14X512Q1A CY14X512Q2A CY14X512Q3A
No
Yes
No
Yes
Yes
No
Yes
Yes
Yes
■
■
Logic Block Diagram
Serial Number
8x8
Manufacturer ID /
Product ID
Power Control
Block
SLEEP
SI
CS
SCK
WP
SO
SPI Control Logic
Write Protection
Instruction decoder
QuantumTrap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
WRSR/RDSR/WREN
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation
Document Number: 001-65267 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 30, 2018
CY14C512Q
CY14B512Q
CY14E512Q
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 5
Software STORE Operation ........................................ 5
Hardware STORE and HSB pin Operation ................. 5
RECALL Operation ...................................................... 5
Hardware RECALL (Power-Up) .................................. 5
Software RECALL ....................................................... 6
Disabling and Enabling AutoStore ............................... 6
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Fast Read Status Register (FAST_RDSR)
Instruction ......................................................................... 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection ......................... 11
Write Enable (WREN) Instruction .............................. 11
Write Disable (WRDI) Instruction .............................. 12
Block Protection ........................................................ 12
Hardware Write Protection (WP) ............................... 12
Memory Access .............................................................. 13
Read Sequence (READ) Instruction .......................... 13
Fast Read Sequence (FAST_READ) Instruction ...... 13
Write Sequence (WRITE) Instruction ........................ 13
nvSRAM Special Instructions ........................................ 15
Software STORE (STORE) Instruction ..................... 15
Software RECALL (RECALL) Instruction .................. 15
AutoStore Enable (ASENB) Instruction ..................... 15
AutoStore Disable (ASDISB) Instruction ................... 15
Special Instructions ....................................................... 16
SLEEP Instruction ..................................................... 16
Serial Number ................................................................. 16
WRSN (Serial Number Write) Instruction .................. 16
RDSN (Serial Number Read) Instruction ................... 17
FAST_RDSN (Fast Serial Number Read)
Instruction ......................................................................... 17
Device ID ......................................................................... 18
RDID (Device ID Read) Instruction ........................... 18
FAST_RDID (Fast Device ID Read) Instruction ........ 19
HOLD Pin Operation ................................................. 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
DC Electrical Characteristics ........................................ 20
Data Retention and Endurance ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 22
AC Test Conditions ........................................................ 22
AC Switching Characteristics ....................................... 23
Switching Waveforms .................................................... 24
AutoStore or Power-Up RECALL .................................. 25
Switching Waveforms .................................................... 26
Software Controlled STORE and RECALL Cycles ...... 27
Switching Waveforms .................................................... 27
Hardware STORE Cycle ................................................. 28
Switching Waveforms .................................................... 28
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagrams .......................................................... 30
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Document History Page ................................................. 33
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ...................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Document Number: 001-65267 Rev. *I
Page 2 of 34
CY14C512Q
CY14B512Q
CY14E512Q
Pinouts
Figure 1. 8-pin SOIC pinout
[2, 3, 4]
CS
1
2
3
4
8
CY14X512Q1A
7
Top View
6
not to scale
5
VCC
HOLD
SCK
SI
CS
1
2
3
4
8
CY14X512Q2A
7
Top View
6
not to scale
5
VCC
HOLD
SCK
SI
SO
WP
VSS
SO
V
CAP
VSS
Figure 2. 16-pin SOIC pinout
NC
1
2
3
4
5
6
7
8
16
15
CY14X512Q3A
14
Top View
13
not to scale
12
11
10
9
VCC
NC
VCAP
SO
SI
SCK
CS
HSB
NC
NC
NC
WP
HOLD
NC
VSS
Pin Definitions
Pin Name
[2, 3, 4]
CS
SCK
SI
SO
WP
HOLD
HSB
I/O Type
Input
Input
Input
Output
Input
Input
Description
Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
Serial Clock. Runs at speeds up to a maximum of f
SCK
. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
Serial Input. Pin for input of all SPI instructions and data.
Serial Output. Pin for output of data through SPI.
Write Protect. Implements hardware write protection in SPI.
HOLD Pin. Suspends Serial Operation.
Input/Output Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high current and then
a weak internal pull up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
No connect
No Connect: This pin is not connected to the die.
Power supply Ground
Power supply Power supply
V
CAP
NC
V
SS
V
CC
Notes
2. HSB pin is not available in 8-pin SOIC packages (CY14X512Q1A/CY14X512Q2A).
3. CY14X512Q1A part does not have V
CAP
pin and does not support AutoStore.
4. CY14X512Q2A part does not have WP pin.
Document Number: 001-65267 Rev. *I
Page 3 of 34
CY14C512Q
CY14B512Q
CY14E512Q
Device Operation
CY14X512Q is a 512-Kbit (SPI) nvSRAM memory with a
nonvolatile element in each memory cell. All the reads and writes
to nvSRAM happen to the SRAM, which gives nvSRAM the
unique capability to handle infinite writes to the memory. The
data in SRAM is secured by a STORE sequence which transfers
the data in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (V
CAP
) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
The 512-Kbit memory array is organized as 64K words × 8 bits.
The memory can be accessed through a standard SPI interface
that enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This nvSRAM chip also supports
104 MHz SPI access speed with a special instruction for read
operation. This device supports SPI modes 0 and 3 (CPOL,
CPHA = 0, 0 and 1, 1) and operates as SPI slave. The device is
enabled using the Chip Select (CS) pin and accessed through
Serial Input (SI), Serial Output (SO), and Serial Clock (SCK)
pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the Status Register. Further,
the HOLD pin is used to suspend any serial communication
without resetting the serial sequence.
CY14X512Q uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, it provides four special instructions that allow access to
four nvSRAM specific functions: STORE, RECALL, AutoStore
Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable you to choose a part which fits in best in their application.
The feature summary is given in
Table 1.
Table 1. Feature Summary
Feature
WP
V
CAP
HSB
AutoStore
Power-Up
RECALL
CY14X512Q1A CY14X512Q2A CY14X512Q3A
Yes
No
No
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Table 1. Feature Summary
(continued)
Feature
Hardware
STORE
Software
STORE
CY14X512Q1A CY14X512Q2A CY14X512Q3A
No
Yes
No
Yes
Yes
Yes
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
READ instruction can be used upto 40 MHz clock speed. The
READ instruction is issued through the SI pin of the nvSRAM and
consists of the READ opcode and two bytes of address. The data
is read out on the SO pin.
A speed higher than 40 MHz (up to 104 MHz) requires
FAST_READ instruction. The FAST_READ instruction is issued
through the SI pin of the nvSRAM and consists of the
FAST_READ opcode, two bytes of address, and one dummy
byte. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14X512Q is inhibited until the cycle is
completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
Page 4 of 34
Document Number: 001-65267 Rev. *I
CY14C512Q
CY14B512Q
CY14E512Q
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes t
STORE
time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready or Busy status of the nvSRAM. After the t
STORE
cycle time
is completed, the SRAM is activated again for read and write
operations.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V
CAP
) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V
CC
to
charge the capacitor connected to the V
CAP
pin. When the
voltage on the V
CC
pin drops below V
SWITCH
during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V
CAP
capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note
If a capacitor is not connected to V
CAP
pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore
Disable (ASDISB) Instruction on page 15).
If
AutoStore is enabled without a capacitor on the V
CAP
pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This will corrupt the data stored in
nvSRAM, Status Register as well as the serial number and it will
unlock the SNL bit. To resume normal functionality, the WRSR
instruction must be issued to update the nonvolatile bits BP0,
BP1, and WPEN in the Status Register.
Figure 3
shows the proper connection of the storage capacitor
(V
CAP
) for AutoStore operation. Refer to
DC Electrical Charac-
teristics on page 20
for the size of the V
CAP
.
Note
CY14X512Q1A does not support AutoStore operation. You
must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Figure 3. AutoStore Mode
V
CC
Hardware STORE and HSB pin Operation
The HSB pin in CY14X512Q3A is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after t
DELAY
duration. A STORE
cycle starts only if a write to the SRAM has been performed since
the last STORE or RECALL cycle. Reads and Writes to the
memory are inhibited for t
STORE
duration or as long as HSB pin
is LOW. The HSB pin also acts as an open drain driver (internal
100 k weak pull up resistor) that is internally driven LOW to
indicate a busy condition when the STORE (initiated by any
means) is in progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by an internal 100 k pull up
resistor.
Note
For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for t
LZHSB
time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
Note
CY14X512Q1A/CY14X512Q2A do not have HSB pin. RDY
bit of the SPI Status Register may be probed to determine the
Ready or Busy status of nvSRAM.
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
0.1 uF
10 kOhm
V
CC
CS
V
CAP
V
CAP
V
SS
Hardware RECALL (Power-Up)
During power-up, when V
CC
crosses V
SWITCH
, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes t
FA
time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the ready status of the device.
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
Document Number: 001-65267 Rev. *I
Page 5 of 34
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