Low Noise Amplifier with
Mitigated Bypass Switch
Data Sheet
Features
• Operating frequency:
0.1 GHz ~ 6.0 GHz
• Noise figure: 0.8 dB (NFmin)
• Gain: 16 dB
• Average Idd = 2mA in CDMA
handset
Description
Agilent’s MGA-71543 is an
economical, easy-to-use GaAs
MMIC Low Noise Amplifier (LNA),
which is designed for adaptive
CDMA and W-CDMA receiver
systems. The MGA-71543 is part
of the Agilent Technologies
complete CDMAdvantage RF
chipset.
The MGA-71543 features a
minimum noise figure of 0.8 dB
and 16 dB available gain from a
single stage, feedback FET
amplifier. The input and output
are partially matched, and only a
simple series/shunt inductor
match is required to achieve low
noise figure and VSWR into 50Ω.
When set into the bypass mode,
both input and output are inter-
nally matched through a mitigative
circuit. This circuit draws no
current, yet duplicates the in and
out impedance of the LNA. This
allows the system user to have
minimum mismatch change from
LNA to bypass mode, which is
very important when the
MGA-71543 is used between
duplexers and/or filters.
The MGA-71543 offers an inte-
grated solution of LNA with
adjustable IIP3. The IIP3 can be
fixed to a desired current level for
the receiver’s linearity require-
ments. The LNA has a bypass
switch function, which provides
low insertion loss at zero current.
The bypass mode also boosts
dynamic range when high level
signal is being received.
The MGA-71543 is designed for
CDMA and W-CDMA receiver
systems. The IP3, Gain, and
mitigative network are tailored to
these applications where filters
are used. Many CDMA systems
operate 20% LNA mode, 80%
bypass. With the bypass current
draw of zero and LNA of 10 mA,
the MGA-71543 allows an average
2 mA current.
The MGA-71543 is a GaAs MMIC,
processed on Agilent’s cost
effective PHEMT (Pseudomorphic
High Electron Mobility Transistor
Technology). It is housed in the
SOT343 (SC70 4-lead) package.
• Bypass switch on chip
Loss = -5.6 dB (Id < 5
µA)
IIP3 = +35 dBm
• Adjustable input IP3: 0 to +9 dBm
• 2.7 V to 4.2 V operation
Applications
• CDMA (IS-95, J-STD-008) Receive
LNA
• Transmit Driver Amp
• W-CDMA Receiver LNA
• TDMA (IS-136) handsets
Surface Mount Package
SOT-343/4-lead SC70
Pin Connections and
Package Marking
3
INPUT
& V
ref
4
1
RF Gnd
& V
s
2
OUTPUT
& V
d
71x
RF Gnd
& V
s
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Functional Block Diagram
Simplified Schematic
+
–
+
–
Control
Input
& V
ref
Gain FET
Output
& V
d
Evaluation
Test Circuit
(single positive bias)
Input
1.5 nH
71
RF IN
RF OUT
2.7 nH
Ou
R
bias
V
d
RF Gnd
& Vs
Switch & Bias
RF Gnd
control
MGA-71543 Absolute Maximum Ratings
[1]
Symbol
V
d
V
c
I
d
P
d
P
in
T
j
T
STG
Parameter
Maximum Input to Output Voltage
[4]
Maximum Input to Ground DC Voltage
[4]
Supply Current
Power Dissipation
[2]
CW RF Input Power
Junction Temperature
Storage Temperature
Units
V
V
mA
mW
dBm
°C
°C
Absolute
Maximum
5.5
+.3
-5.5
60
240
+15
170
-65 to +150
Operation
Maximum
4.2
+.1
-4.2
50
200
+10
150
-40 to +85
Thermal Resistance:
[2, 3]
θ
jc
= 240°C/W
Notes:
1. Operation of this device in excess of any o
these limits may cause permanent damag
2. Ground lead temperature at 25°C.
3. Thermal resistance measured by 150°C
Liquid Crystal Measurement method.
4. Maximum rating assumes other paramete
are at DC quiescent conditions.
Product Consistency Distribution Charts
[5,6]
150
Cpk = 2.00
Std = 0.24
150
Cpk = 1.16
Std = 0.96
150
Cpk = 2.33
Std = 0.02
120
120
120
FREQUENCY
FREQUENCY
FREQUENCY
90
-3 Std
+3 Std
90
-3 Std
+3 Std
90
-3 Std
+3 Std
60
60
60
30
30
30
0
14.4
0
15.4
GAIN (dB)
16.4
17.4
1
2
3
4
5
6
7
8
IIP3 (dBm)
0
0.85
0.95
1.05
1.15
NF (dB)
1.25
1.35
1.
Figure 1. Gain @ 2 GHz, 3V, 10 mA.
LSL = 14.4, Nominal = 15.9, USL = 17.4
Figure 2. IIP3 @ 2 GHz, 3V, 10 mA.
LSL = 1.0, Nominal = 4.3, USL = 8.0
Figure 3. NF @ 2 GHz, 3V, 10 mA.
LSL = 0.85, Nominal = 1.08, USL = 1.45
Notes:
5. Distribution data sample size is 450 samples
taken from 9 different wafers. Future wafers
allocated to this product may have nominal
values anywhere within the upper and lower
specification limits.
6. Measurements made on production test
board, Figure 4. This circuit represents a
trade-off between an optimal noise match
and a realizable match based on production
test requirements at 10 mA bias current.
Excess circuit losses have been de-
embedded from actual measurements.
Performance may be optimized for different
bias conditions and applications. Consult
Application Note for details.
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MGA-71543 Electrical Specifications
T
c
= +25°C, Z
o
= 50Ω, I
d
= 10 mA, V
d
= 3V, unless noted
Symbol
Vref test
NF test
Gain test
IIP3 test
Gain, Bypass
Ig test
NFmin
[3]
Parameter and Test Condition
Vds = 2.4 V
f = 2.01 GHz
f = 2.01 GHz
f = 2.01 GHz
V
d
= 3.0 V (= Vds - Vref)
V
d
= 3.0 V (= Vds - Vref)
V
d
= 3.0 V (= Vds - Vref)
I
d
= 10 mA
I
d
= 10 mA
I
d
= 10 mA
I
d
= 10 mA
I
d
= 0 mA
I
d
= 0 mA
f = 0.9 GHz
f = 1.5 GHz
f = 1.9 GHz
f = 2.1 GHz
f = 2.5 GHz
f = 6.0 GHz
f = 0.9 GHz
f = 1.5 GHz
f = 1.9 GHz
f = 2.1 GHz
f = 2.5 GHz
f = 6.0 GHz
I
d
= 0 mA
I
d
= 3 mA
I
d
= 6 mA
I
d
= 10 mA
I
d
= 20 mA
I
d
= 40 mA
I
d
= 0 mA
I
d
= 3 mA
I
d
= 6 mA
I
d
= 10 mA
I
d
= 20 mA
I
d
= 40 mA
Intrinsic
Eval Circuit
f = 2.01 GHz
f = 2.01 GHz
f = 2.01 GHz
Units
V
dB
dB
dBm
dB
µA
dB
Min.
-0.86
Typ.
-0.65
1.1
Max.
-0.43
1.45
17.4
σ
[1
0.041
0.02
0.24
0.96
0.12
1.5
14.4
1
-6.4
15.9
4.3
-5.6
2.0
0.7
0.7
0.8
0.8
0.8
1.1
17.1
16.4
15.8
15.4
14.9
10.0
+10
-5.1
+3.0
+7.4
+13.1
+15.5
+35
-2.6
+1.6
+4.3
+7.4
+8.7
10
100
6.0
10.9
-22.5
f = 2.01 GHz
Vds = 0 V, Vref = -3V
[6]
Bypass Mode
Bypass Mode Vds = 0 V, Vref = -3 V
[6]
Minimum Noise Figure
As measured in Figure 5 Test Circuit
(Γopt computed from s-parameter and
noise parameter performance as measured
in a 50Ω impedance fixture)
Associated Gain at Nfo
As measured in Figure 5 Test Circuit
(Gopt computed from s-parameter and
noise parameter performance as measured
in a 50Ω impedance fixture)
Output Power at 1 dB Gain Compression
As measured in Evaluation Test Circuit with
source resistor biasing
[4,5]
Frequency = 2.01 GHz
Gass
[3]
dB
P1dB
dBm
IIP3
Input Third Order Intercept Point
As measured in Figure 4 Test Circuit
[5]
Frequencies = 2.01 GHz, 2.02 GHz
dBm
Switch
Bypass Switch Rise/Fall Time
(10% - 90%)
As measured in Evaluation Test Circuit
Input Return Loss as measured in Fig. 4
Output Return Loss as measured in Fig. 4
Isolation |s12|
2
as measured in Fig. 5
nS
dB
dB
dB
RLin
RLout
ISOL
0.31
0.65
Notes:
1. Standard Deviation and Typical Data based at least 450 part sample size from 9 wafers. Future wafers allocated to this product may have nominal
values anywhere within the upper and lower spec limits.
2. Measurements made on a fixed tuned production test circuit (Figure 4) that represents a trade-off between optimal noise match, maximum gain
match, and a realizable match based on production test board requirements at 10 mA bias current. Excess circuit losses have been de-embedded
from actual measurements. Vd=Vds-Vref where Vds is adjusted to maintain a constant Vd bias equivalent to a single supply 3V bias application.
Consult Applications Note for circuit biasing options.
3. Minimum Noise Figure and Associated Gain data computed from s-parameter and noise parameter data measured in a 50Ω system using ATN NP
test system. Data based on 10 typical parts from 9 wafers. Associated Gain is the gain when the product input is matched for minimum Noise Figur
4. P1dB measurements were performed in the evaluation circuit with source resistance biasing. As P1dB is approached, the drain current is
maintained near the quiescent value by the feedback effect of the source resistor in the evaluation circuit. Consult Applications Note for circuit
biasing options.
5. Measurements made on a fixed tuned production test circuit that represents a trade-off between optimal noise match, maximum gain match, and
realizable match based on production test board requirements at 10 mA bias current. Performance may be optimized for different bias conditions
and applications. Consult Applications Note.
6. The Bypass Mode test conditions are required only for the production test circuit (Figure 4) using the gate bias method. In the preferred source
resistor bias configuration, the Bypass Mode is engaged by presenting a DC open circuit instead of the bias resistor on Pin 4.
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T
c
= 25°C, Z
o
= 50, V
d
= 3V, I
d
= 10 mA unless stated otherwise. Data vs. frequency was measured in Figure 5 test system
and was optimized for each frequency with external tuners.
960 pF
RF
Input
56 pF
1.5 nH
2.7 nH
V
ref
4
3
V
ds
56 pF
1
2
RF
Output
56 pF
RF
Input
Bias Tee
Test Fixture
Bias
Tee
V
ds
71
V
ref
RF
Output
Figure 4. MGA-71543 Production Test Circuit.
71
3.9 nH
Figure 5. MGA-71543 Test Circuit for S, Noise, and
Power Parameters over Frequency.
20
18
15
1.5
ASSOCIATED GAIN (dB)
1.3
17
NOISE FIGURE (dB)
1.1
14
INPUT IP3 (dBm)
12
9
6
3
0.9
11
0.7
2.7V
3.0V
3.3V
8
2.7V
3.0V
3.3V
0
-3
2.7V
3.0V
3.3V
0.5
0
1
2
3
4
5
6
FREQUENCY (GHz)
5
0
1
2
3
4
5
6
FREQUENCY (GHz)
0
1
2
3
4
5
6
FREQUENCY (GHz)
Figure 6. Minimum Noise Figure vs.
Frequency and Voltage.
20
-40°C
+25°C
+85°C
Figure 7. Associated Gain with Fmin vs.
Frequency and Voltage.
18
15
Figure 8. Input Third Order Intercept Point vs
Frequency and Voltage.
ASSOCIATED GAIN (dB)
17
INPUT IP3 (dBm)
12
m3
9
6
m2
3
-40°C
+25°C
+85°C
14
11
8
0
5
0
1
2
3
4
5
6
FREQUENCY (GHz)
-3
0
1
2
3
4
m1
5
6
500 MHz to 6 GHz
FREQUENCY (GHz)
Figure 9. Associated Gain with Fmin vs.
Frequency.
Figure 10. Input Third Order Intercept Point
vs. Frequency and Temperature.
0
Figure 11. S11 Impedance vs. Frequency.
(m1 = Sw, m2 = 6 mA, m3 = 10 mA)
18
15
-2
INSERTION LOSS (dB)
12
-4
OP1dB (dBm)
9
6
3
m3
m2 m1
-6
-8
G
ass
w/Fmin
Minimum
0
-3
2.7V
3.0V
3.3V
-10
0
500 MHz to 6 GHz
1
2
3
4
5
6
FREQUENCY (GHz)
0
1
2
3
4
5
6
FREQUENCY (GHz)
Figure 12. S22 Impedance vs. Frequency.
(m1 = Sw, m2 = 6 mA, m3 = 10 mA)
4
Figure 13. Bypass Mode Associated
Insertion Loss with Fmin Match and
Minimum Loss vs. Frequency.
4
Figure 14. Output Power at 1 dB Compression
vs. Frequency and Voltage.
[4]
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MGA-71543 Typical Performance,
continued
T
c
= 25°C, Z
o
= 50, V
d
= 3V, I
d
= 10 mA unless stated otherwise. Data vs. frequency was measured in Figure 5 test system
and was optimized for each frequency with external tuners.
18
15
INPUT IP3 (dBm)
12
OP1dB (dBm)
9
6
3
0
-3
0
1
2
3
4
5
6
FREQUENCY (GHz)
6 mA
10 mA
20 mA
18
15
12
9
-6
3
0
-3
0
10
20
I
dsq
CURRENT (mA)
30
40
-40°C
+25°C
+85°C
18
15
12
OP1dB (dBm)
9
6
3
0
-3
0
10
20
I
d
CURRENT (mA)
30
-40°C
+25°C
+85°C
4
Figure 15. Input Third Order Intercept Point
vs. Frequency and Current.
2.2
2.0
1.8
1.6
1.2
1.0
0.8
0.6
0.4
0.2
0
0
10
20
I
d
CURRENT (mA)
30
40
1.4
NF (dB)
Figure 16. Output Power at 1 dB Compression
vs. I
dsq
Current and Temperature (Passive
Bias, V
ref
Fixed)
[4]
.
20
17
14
GAIN (dB)
11
8
5
2
0
10
20
I
d
CURRENT (mA)
30
40
-40°C
+25°C
+85°C
Figure 17. Output Power at 1 dB Compres
vs. Current and Temperature (Source Res
Bias in Evaluation Circuit)
[5]
.
12
9
INPUT IP3 (dBm)
6
3
-40°C
+25°C
+85°C
0
-3
0
10
20
I
d
CURRENT (mA)
30
Figure 18. Minimum Noise Figure vs. Current
(2 GHz).
1.0
Figure 19. Gain vs. Current and Temperature
(2 GHz).
Figure 20. Input Third Intercept Point vs.
Current and Temperature (2 GHz).
0.8
Vs (V)
0.6
0.4
0.2
0
0
10
20
I
d
CURRENT (mA)
30
40
Figure 21. Control Voltage vs. Current.
Notes:
4. P1dB measurements were performed with
passive biasing in Production Test Circuit
(Figure 4.). Quiescent drain current, Idsq, is
set by a fixed Vref with no RF drive applied.
As P1dB is approached, the drain current
may increase or decrease depending on
frequency and DC bias point which typically
results in higher P1dB than if the drain
current is maintained constant by active
biasing.
5. P1dB measurements were performed in
Evaluation Test Circuit with source resistor
biasing which maintains the drain current
near the quiescent value under large signal
conditions.
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