74LVC132A
Quad 2-input NAND Schmitt trigger
Rev. 3 — 7 December 2011
Product data sheet
1. General description
The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is
capable of transforming slowly-changing input signals into sharply defined, jitter-free
output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
T+
and the negative voltage V
T
is defined as the input
hysteresis voltage V
H
.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V environment.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
5 V tolerant inputs for interfacing with 5 V logic
CMOS low-power consumption
Direct interface with TTL levels
Unlimited input rise and fall times
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrator
Monostable multivibrator.
NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC132AD
40 C
to +125
C
Name
SO14
TSSOP14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
74LVC132APW
40 C
to +125
C
74LVC132ABQ
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
5. Functional diagram
1
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2
4
2Y 6
5
9
10
12
13
mna212
&
3
&
6
3Y 8
&
8
A
4Y 11
&
mna246
11
B
Y
001aac532
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
74LVC132A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
2 of 16
NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
74LVC132A
terminal 1
index area
14 V
CC
13 4B
12 4A
11 4Y
GND(1)
7
8
10 3B
9
GND
3Y
3A
1A
2
3
4
5
6
1
1B
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aaf590
74LVC132A
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
2Y
1Y
2A
2B
001aaf591
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
74LVC132A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
3 of 16
NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
7. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[4]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
[2][3]
Min
0.5
0.5
0.5
50
-
-
-
100
65
Max
+6.5
+6.5
V
CC
+ 0.5
-
50
50
100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
T
amb
=
40 C
to +125
C
[4]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
For SO14 packages: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
9. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
Conditions
Min
1.65
1.2
0
0
40
Typ
-
-
-
-
-
Max
3.6
-
5.5
V
CC
+125
Unit
V
V
V
V
C
74LVC132A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
4 of 16
NXP Semiconductors
74LVC132A
Quad 2-input NAND Schmitt trigger
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
40 C
to +85
C
V
OH
HIGH-level output voltage
V
I
= V
T+
or V
T
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
T+
or V
T
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
CC
I
CC
C
I
V
OH
input leakage current
supply current
additional supply current
input capacitance
HIGH-level output voltage
V
CC
= 3.6 V; V
I
= 5.5 V or GND
V
CC
= 3.6 V; V
I
= V
CC
or GND; I
O
= 0 A
per input pin; V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
V
CC
= 0 V to 3.6 V; V
I
= GND to V
CC
V
I
= V
T+
or V
T
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
T+
or V
T
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
CC
I
CC
input leakage current
supply current
additional supply current
V
CC
= 3.6 V; V
I
= 5.5 V or GND
V
CC
= 3.6 V; V
I
= V
CC
or GND; I
O
= 0 A
per input pin; V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
40
5
V
V
V
V
V
A
A
mA
V
CC
0.3
V
CC
0.6
-
-
-
-
-
-
-
-
V
V
V
V
V
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
5
4.0
0.2
0.45
0.6
0.4
0.55
5
10
500
-
V
V
V
V
V
A
A
A
pF
V
CC
0.2
V
CC
0.5
V
CC
0.5
V
CC
0.6
V
CC
0.8
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
CC
0.45 -
Conditions
Min
Typ
[1]
Max
Unit
T
amb
=
40 C
to +125
C
V
CC
0.65 -
V
CC
0.65 -
V
CC
0.75 -
V
CC
1
-
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
C.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
74LVC132A
Product data sheet
Rev. 3 — 7 December 2011
5 of 16
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