Si 5 3 4 5 / 4 4 /4 2
1 0 - C
H A N N E L
, A
NY
-F
R E Q U E N C Y
, A
NY
- O
U T P U T
J
I T T E R
A
T T E N U A T O R
/C
LOC K
M
U LT IP L IE R
Features
IN3/FB_IN
IN3/FB_IN
Generates any combination of
output frequencies from any input
frequencies
Input frequency range:
Differential: 8 kHz to 750 MHz
LVCMOS: 8 kHz to 250 MHz
Output frequency range:
Differential: up to 800 MHz
LVCMOS: up to 250 MHz
Jitter performance:
<100 fs typ (12 kHz–20 MHz)
Programmable jitter attenuation
bandwidth: 0.1 Hz to 4 kHz
Meets G.8262 EEC Opt 1, 2 (SyncE)
Highly configurable outputs
compatible with LVDS, LVPECL,
LVCMOS, HCSL, or programmable
voltage swing and common mode
Status monitoring (LOS, OOF, LOL)
Hitless input clock switching:
automatic or manual
Locks to gapped clock inputs
Automatic free-run and holdover
modes
Optional zero delay mode
Fastlock feature: <200 ms lock time
Glitchless on the fly output
frequency changes
DCO mode: as low as 0.001 ppb
steps.
Core voltage
V
DD
: 1.8 V ±5%
V
DDA
:
3.3 V ±5%
Independent output supply pins:
3.3 V, 2.5 V, or 1.8 V
Output-output skew: <100 ps
Serial interface:
or SPI
In-circuit programmable with
non-volatile OTP memory
ClockBuilder Pro
TM
software
simplifies device configuration
Si5345: 4 input, 10 output, 64 QFN
Si5344: 4 input, 4 output, 44 QFN
Si5342: 4 input, 2 output, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
I
2
C
Ordering Information:
See section 7
Pin Assignments
Si5345
Top View
VDDO9
VDDO8
RSVD
RSVD
OUT8
VDDO7
49
OUT9
OUT9
OUT8
OUT7
51
64
63
62
61
60
59
58
57
56
55
54
53
52
IN1
IN1
IN_SEL0
IN_SEL1
RSVD
RST
X1
XA
XB
X2
OE
INTR
VDDA
IN2
IN2
50
OUT7
VDD
IN0
IN0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
FINC
LOL
VDD
OUT6
OUT6
VDDO6
OUT5
OUT5
VDDO5
I2C_SEL
OUT4
OUT4
VDDO4
OUT3
OUT3
VDDO3
GND
Pad
41
40
39
38
37
36
35
34
33
Applications
OTN Muxponders and
Transponders
10/40/100G network line cards
GbE/10GbE/100GbE Synchronous
Ethernet
IN3/FB_IN
IN3/FB_IN
VDD
I2C_SEL
IN_SEL1
44
43
42
41
40
39
38
37
36
35
IN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
34
VDDO3
Carrier Ethernet switches
SONET/SDH Line Cards
Broadcast video
Test and measurement
SCLK
RSVD
SDA/SDIO
A1/SDO
RSVD
FDEC
OUT0
OUT0
OUT1
OUT1
OUT2
33
32
31
30
29
28
27
26
25
24
23
VDDO0
VDDO1
Si5344 44QFN
Top View
OUT3
OUT3
IN0
IN0
VDD
VDDO2
A0/CS
33
32
31
30
29
OUT2
INTR
VDD
OUT2
OUT2
VDDO2
LOS_XAXB
LOL
VDDS
OUT1
OUT1
VDDO1
Description
These jitter attenuating clock multipliers combine fourth-generation DSPLL and
MultiSynth™ technologies to enable any-frequency clock generation and jitter
attenuation for applications that require the highest level of jitter performance.
These devices are programmable via a serial interface with in-circuit
programmable non-volatile memory (NVM) so that they always power up with a
known frequency configuration. They support free-run, synchronous, and
holdover modes of operation, and offer both automatic and manual input clock
switching. The loop filter is fully integrated on-chip eliminating the risk of potential
noise coupling associated with discrete solutions. Further, the jitter attenuation
bandwidth is digitally programmable providing jitter performance optimization at
the application level. Programming the Si5345/44/42 is made easy with Silicon
Labs’
ClockBuilderPro
software. Factory preprogrammed devices are also
available.
IN1
IN_SEL0
X1
XA
XB
X2
VDDA
VDDA
IN2
IN2
GND
Pad
28
27
26
25
24
23
A1/SDO
OUT0
OE
SDA/SDIO
Si5342 44QFN
Top View
IN3/FB_IN
IN3/FB_IN
VDD
I2C_SEL
IN_SEL1
VDDS
LOS3
LOS2
IN0
IN0
VDD
44
43
42
41
40
39
38
VDDO0
A0/CS
SCLK
37
36
OUT0
35
VDD
RST
IN1
IN1
IN_SEL0
X1
XA
XB
X2
VDDA
VDDA
IN2
IN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
34
NC
INTR
VDD
LOS1
LOS0
VDDS
LOS_XAXB
LOL
VDDS
OUT1
OUT1
VDDO1
GND
Pad
OUT0
VDD
OE
SDA/SDIO
A1/SDO
VDDO0
Preliminary Rev. 0.9 7/14
Copyright © 2014 by Silicon Laboratories
A0/CS
SCLK
OUT0
RST
NC
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
VDD
Si5345/44/42
Si5345/44/42
T
ABLE
O
F
C
ON TENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.12. Custom Factory-Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . 48
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Appendix—Advance Product Information Revision History . . . . . . . . . . . . . . . . . . . . . . . 53
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Preliminary Rev. 0.9
3
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
