3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q32C
GD25Q32C
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q32C
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES .................................................................................................................................................. 4
GENERAL DESCRIPTION .......................................................................................................................... 5
MEMORY ORGANIZATION ......................................................................................................................... 7
DEVICE OPERATION .................................................................................................................................. 8
DATA PROTECTION ................................................................................................................................... 9
STATUS REGISTER .................................................................................................................................. 11
COMMANDS DESCRIPTION .................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
W
RITE
E
NABLE
(WREN) (06H) ............................................................................................................. 16
W
RITE
D
ISABLE
(WRDI) (04H) .............................................................................................................. 16
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) ........................................................................ 17
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H
OR
15H) ...................................................................... 18
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H
OR
31H
OR
11H) .................................................................... 18
R
EAD
D
ATA
B
YTES
(READ) (03H) ........................................................................................................ 19
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) ..................................................................... 19
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) .......................................................................................................... 20
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ......................................................................................................... 21
7.10. D
UAL
I/O F
AST
R
EAD
(BBH) ................................................................................................................. 21
7.11. Q
UAD
I/O F
AST
R
EAD
(EBH) ................................................................................................................. 23
7.12. Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) ...................................................................................................... 24
7.13. S
ET
B
URST WITH
W
RAP
(77H) .............................................................................................................. 26
7.14. P
AGE
P
ROGRAM
(PP) (02H) ................................................................................................................. 27
7.15. Q
UAD
P
AGE
P
ROGRAM
(32H)................................................................................................................ 28
7.16. F
AST
P
AGE
P
ROGRAM
(FPP) (F2H) ...................................................................................................... 29
7.17. S
ECTOR
E
RASE
(SE) (20H) .................................................................................................................. 30
7.18. 32KB B
LOCK
E
RASE
(BE) (52H) ........................................................................................................... 30
7.19. 64KB B
LOCK
E
RASE
(BE) (D8H) .......................................................................................................... 31
7.20. C
HIP
E
RASE
(CE) (60/C7H) .................................................................................................................. 31
7.21. D
EEP
P
OWER
-D
OWN
(DP) (B9H) .......................................................................................................... 32
7.22. R
ELEASE FROM
D
EEP
P
OWER
-D
OWN OR
H
IGH
P
ERFORMANCE
M
ODE AND
R
EAD
D
EVICE
ID (RDI) (ABH) 33
7.23. R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H) .............................................................................. 34
7.24. D
UAL
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (92H) ............................................................................. 35
7.25. Q
UAD
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (94H)............................................................................. 36
7.26. R
EAD
I
DENTIFICATION
(RDID) (9FH) ..................................................................................................... 37
7.27. H
IGH
P
ERFORMANCE
M
ODE
(HPM) (A3H) ............................................................................................. 38
7.28. R
EAD
U
NIQUE
ID (4BH) ........................................................................................................................ 39
7.29. P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) .............................................................................................. 40
7.30. P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH)............................................................................................... 41
7.31. E
RASE
S
ECURITY
R
EGISTERS
(44H) ...................................................................................................... 41
7.32. P
ROGRAM
S
ECURITY
R
EGISTERS
(42H) ................................................................................................. 42
2
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q32C
7.33. R
EAD
S
ECURITY
R
EGISTERS
(48H)........................................................................................................ 43
7.34. E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ............................................................................................... 44
7.35. R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ........................................................................ 44
8.
ELECTRICAL CHARACTERISTICS ......................................................................................................... 49
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
9.
POWER-ON TIMING .......................................................................................................................... 49
INITIAL DELIVERY STATE................................................................................................................. 49
ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 49
CAPACITANCE MEASUREMENT CONDITIONS .............................................................................. 51
DC CHARACTERISTICS .................................................................................................................... 52
AC CHARACTERISTICS .................................................................................................................... 55
ORDERING INFORMATION ...................................................................................................................... 62
9.1.
V
ALID
P
ART
N
UMBERS
.......................................................................................................................... 63
PACKAGE INFORMATION .................................................................................................................... 65
10.
10.1. P
ACKAGE
SOP8 150MIL ...................................................................................................................... 65
10.2. P
ACKAGE
SOP8 208MIL ...................................................................................................................... 66
10.3. P
ACKAGE
VSOP8 208MIL .................................................................................................................... 67
10.4. P
ACKAGE
DIP8 300MIL ........................................................................................................................ 68
10.5. P
ACKAGE
USON8 (3*3
MM
) ................................................................................................................... 69
10.6. P
ACKAGE
USON8 (3*4
MM
) ................................................................................................................... 70
10.7. P
ACKAGE
WSON8 (6*5
MM
) .................................................................................................................. 71
10.8. P
ACKAGE
TFBGA-24BALL (6*4
BALL ARRAY
) ....................................................................................... 72
10.9. P
ACKAGE
TFBGA-24BALL (5*5
BALL ARRAY
) ....................................................................................... 73
11.
REVISION HISTORY.............................................................................................................................. 74
3
3.3V Uniform Sector
Dual and Quad Serial Flash
1.
FEATURES
◆Fast
Program/Erase Speed
GD25Q32C
◆32M-bit
Serial Flash
-4096K-Byte
-256 Bytes per programmable page
◆Standard,
Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆High
Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
◆Software/Hardware
Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top/Bottom Block protection
◆Minimum
100,000 Program/Erase Cycles
◆Data
Retention
-20-year data retention typical
◆Allows
XIP (execute in place) Operation
-Continuous Read With 8/16/32/64-Byte Wrap
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.15/0.25s typical
-Chip Erase time: 15s typical
◆Flexible
Architecture
-Uniform Sector of 4K-Byte
-Uniform Block of 32/64K-Byte
◆Low
Power Consumption
-1μA typical deep power down current
-1μA typical standby current
◆Advanced
Security Features
(1)
-128-bit Unique ID
-3x1024-Byte Security Registers With OTP Locks
-Discoverable parameters (SFDP) register
◆Single
Power Supply Voltage
-Full voltage range: 2.7~3.6V
◆Package
Information
-SOP8 (208mil)
-SOP8 (150mil)
-VSOP8 (208mil)
-DIP8 (300mil)
-WSON8 (6*5mm)
-USON8 (3*3mm)
-USON8 (3*4mm)
-TFBGA-24 (6*4 ball array)
-TFBGA-24 (5*5ball array)
Note: 1.Please contact GigaDevice for details.
4
3.3V Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25Q32C
The GD25Q32C (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
CONNECTION DIAGRAM
CS#
SO
(IO1)
WP#
(IO2)
VSS
1
2
Top View
3
4
6
5
8
7
VCC
HOLD#
(IO3)
SCLK
SI
(IO0)
CS#
SO
(IO1)
WP#
(IO2)
1
2
Top View
3
8
7
VCC
HOLD#
(IO3)
6 SCLK
5
8–LEAD WSON/USON
SI
(IO0)
VSS 4
8–LEAD SOP/VSOP/DIP
Top View
Top View
5
NC
NC
NC
NC
NC
NC
NC
4
NC
VCC
VSS
SCLK
WP# HOLD#
(IO2) (IO3)
NC
NC
4
NC
VCC
VSS
SCLK
WP#
HOLD#
(IO2)
(IO3)
NC
SI(IO0)
3
NC
NC
SI(IO0)
NC
3
NC
NC
NC
2
NC
CS# SO(IO1) NC
2
NC
CS# SO(IO1) NC
1
NC
NC
NC
NC
NC
NC
1
NC
NC
NC
NC
A
B
C
D
E
A
B
C
D
E
F
24-BALL TFBGA (5x5 ball array)
24-BALL TFBGA (6x4 ball array)
PIN DESCRIPTION
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5