DRC-11522
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®
TWO-CHANNEL DIGITAL-TO-RESOLVER
CONVERTER
FEATURES
•
16-Bit Resolution
•
Pin Programmable Gain Control
•
Two Channels in One 36-Pin DDIP
•
Accuracy to 2 Min.
•
0.1% Scale Factor Variation with
Angle
•
DC-Coupled Reference
•
High Reliability CMOS D/R Chip
•
8-Bit/2-Byte Double-Buffered
Transparent Latches
DESCRIPTION
The DRC-11522 is a dual 16-bit Digital-to-Resolver (D/R) converter.
Each channel is independent from the other with the exception of the
16 digital lines. The DRC-11522 allows the user to program the gain
of the resolver output.
Packaged in a 36-pin double DIP, the DRC-11522 is two Digital-to-
Resolver converters in one hybrid module. Using an AC reference
input, the DRC-11522 is a Digital-to-Resolver converter. When using
a DC reference input, the unit can be used as a hybrid Digital-to-
SIN/COS DC converter. With the reference input proportional to the
radius vector, the DRC-11522 converts polar to rectangular coordi-
nates.
The circuit design in the DRC-11522 allows for higher accuracy and
reduces the output scale factor variation so that the output can drive
displays directly. The output line-to-line voltage can be scaled by pin
programming. Other features include buffered reference input, and a
wide operating temperature range.
APPLICATIONS
Because of its high reliability, small size and low power consumption,
the DRC-11522 is ideal for the most stringent and severe industrial
and military ground or avionics applications. All units are available
with MIL-PRF-38534 processing.
Among the many possible applications are computer-based systems
in which digital information is processed, such as simulators, flight
trainers, flight instrumentation, fire control systems, radar and navi-
gation systems.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
©
1988, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
SIN B
OUTPUT
AMPLIFIERS
OUTPUT
AMPLIFIERS
COS B
REFERENCE CONDITIONER
+C
+S
+C
+S
-
REF
+
Ref In (+)
GC1-B
Gain
Program
Pins
GC2-B
D/R CONVERTER
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
D/R CONVERTER
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
TRANSPARENT
LATCH
TRANSPARENT
LATCH
TRANSPARENT
LATCH
TRANSPARENT
LATCH
Ref In (-)
LA-A LM-A
LL-A LL-B
LM-B LA-B
+15 V
-15 V
GND
DIGITAL INPUT
SIN A
COS A
REFERENCE CONDITIONER
-
REF
Ref In (+)
+
GC1-A
Gain
Program
Pins
GC2-A
2
Ref In (-)
FIGURE 1. DRC-11522 BLOCK DIAGRAM
DRC-11522
R-12/06-0
TABLE 1. SPECIFICATIONS (FOR EACH CHANNEL)
Apply over temperature range, power supply ranges, reference voltage, and frequency range, and 10% harmonic distortion in the reference.
PARAMETER
RESOLUTION
ACCURACY
Output Accuracy
Differential Linearity
Radius accuracy
DYNAMICS
Output Settling Time
DIGITAL INPUT
Logic Type
VALUE
16 bits (0.33 arc minutes)
4 minutes to 2 minutes + 1 LSB
(see ordering info)
±1 LSB max
±0.03%
DESCRIPTION/REMARKS
MSB = 180° LSB = 0.0055°
Accuracy applies over operating temp. range
Simultaneous amplitude variation in both
outputs as a function of digital angle
For any analog or digital step change
Less than 20 µsec for any digital step change.
Natural binary angle parallel positive logic CMOS
and TTL compatible.
Inputs are CMOS transient protected. Each input
has a 20 µa max pull down to GND.
0 VDC to 0.8 VDC
+2.0 VDC to 1/3 of V
DD
+ 10%
65 µA max
20 µA
External logic voltage not needed. TTL compatible.
Bits 1-16
LL, LM, LA (See timing Diagram, FIGURE 2)
Logic “0”
Logic “1”
Load Current
REFERENCE INPUT
Type
Frequency Range
Voltage
Input Impedance
ANALOG OUTPUT
Type
Output Current
Max Output Voltage (Tracks
Reference Input Voltage)
Converter Gain (K)
Transformation Ratio Tol.
Scale Factor Variation
DC Offset
POWER SUPPLIES
Voltage
Max Voltage Without Damage
Current or Impedance
TEMPERATURE RANGES (CASE)
Operating
-1 Option
-3 Option
Storage
PHYSICAL CHARACTERISTICS
Type
Size
Weight
DC to 1000 Hz
3.5 V ±10%
10 M Ohm min
Programmable (See TABLE 2.)
0 to ±10 peak AC or DC
Operational Amplifier Buffer
Resolver
2 mA rms max
K * Vin * Sin q also K * Vin * Cos q
0.5, 1.0, or 2.0 ±1%
±1% max
±0.1% max
±10 mV typical, ±25 mV max
±15 VDC ±10%
±18 VDC
±40 mA max
±10 V peak AC or DC
See TABLE 2.
Each Line to GND
For ±10 V peak output
-55°C to +125°C
0°C to +70°C
-60°C to +135°C
36-pin double DIP
0.78 x 1.9 x 0.21 inch
(2.0 x 4.8 x 0.53 cm)
0.6 oz (17g) max
Data Device Corporation
www.ddc-web.com
3
DRC-11522
R-12/06-0
TECHNICAL INFORMATION
DIGITAL INPUTS
For each channel, the 16-bit digital angle is double buffered with
transparent latches (See FIGURE 1). The latch controls have
internal pull-up current sources to +5 V, this puts the latches in
the transparent mode when they are not connected.
The angle is determined by adding the logic bits. The enable
inputs are LL (1st Latch LSBs), LM (1st Latch MSBs), and LA
(2nd Latch All); see FIGURES 2A & 2B for timing.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN
TABLE 3. PINOUTS
FUNCTION
LL-B
COS A
SIN A
GC1-B
GC2-B
Ref B
GC1-A
GC2-A
Ref A
COS B
SIN B
NC
+15 V
-15 V
LA-B
LA-A
LL-A
GND
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PIN
FUNCTION
Bit 16 (LSB)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (MSB)
LM-A
LM-B
OUTPUT SCALING AND REFERENCE LEVEL
ADJUSTMENT
The DRC-11522 operates like a multiplying D/A converter in that
the voltage of each output line is directly proportional to the ref-
erence voltage. The maximum line-to-line levels are determined
by the output amplifiers and are programmable for a gain of 0.5,
1.0, or 2.0 (See TABLE 2.).
TABLE 2. PROGRAMMABLE GAIN
GC1-A
(PIN 7)
GND
OPEN
OPEN
GC1-B
(PIN 4)
GC2-A
(PIN 8)
OPEN
GND
OPEN
GC2-B
(PIN 5)
GAIN
(K)
0.5
1.0
2.0
GAIN
(K)
NOTE: Functions LL, LM, LA both A and B may be left unconnected
when not used.
TABLE 4. PIN DEFINITIONS
PIN
GND
DEFINITION
Power Supply Ground
Digital Ground
Analog Signal Ground
Digital Input bits, B1 = MSB = 180 degrees
High Byte Enable (B1-B8) for MSB’s 8-bit Input register of
channel A. Logic high enables, low holds.
High Byte Enable (B1-B8) for MSB’s 8-bit Input register
channel B Logic high enables, low holds.
Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of
channel A. Logic high enables, low holds
Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of
channel B. Logic high enables, low holds.
Channel A Load Converter. Logic high transfers Channel
A input registers data into 16-bit holding register. When
low, Channel A is in hold mode.
Channel B Load Converter. Logic high transfers Channel
B input registers data into 16-bit holding register. When
low, Channel B is in hold mode.
Power Supply Voltage.
Power Supply Voltage.
CAUTION:
REVERSAL OF POWER SUPPLIES
WILL DAMAGE THE CONVERTER.
Channel A reference voltage input
Channel B reference voltage input
Channel A gain programming pin
Channel A gain programming pin
Channel B gain programming pin
Channel B gain programming pin
Analog output of Channel A
Analog output of Channel A
Analog output of Channel B
Analog output of Channel B
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
sin = (REF * K) Ao [1 + A(q)] sin q
cos = (REF * K) Ao [1 + A(q)] cos q
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (REF * K). The
transformation ratio Ao is determined by the programmable gain
inputs (0.5, 1.0, or 2.0). The maximum variation in Ao from all
causes is 0.1%. The term A(q) represents the variation of the
amplitude with the digital signal input angle. A(q), which is called
the scale factor variation, is a smooth function of (q) without dis-
continuities and is less than ±0.1% for all values of (q). The total
maximum variation in Ao[1 + A(q)] is therefore ±0.2%.
Because the amplitude factor (REF * K) Ao [1 + A(q)] varies
simultaneously on all output lines, it is not a source of error when
the DRC-11522 is driving a ratiometric system. However, if the
outputs are used independently, as in x-y plotters, the amplitude
variations must be taken into account.
B1-B16
LM-A
LM-B
LL-A
LL-B
LA-A
LA-B
+15 V
-15 V
Ref-A
Ref-B
GC1-A
GC2-A
GC1-B
GC2-B
Sin A
Cos A
Sin B
Cos B
Data Device Corporation
www.ddc-web.com
4
DRC-11522
R-12/06-0
POWER SUPPLY CYCLING
Power supply cycling of the DDC converter should follow the
guidelines below to avoid any potential problems. Strictly main-
tain proper sequencing of supplies and signals per typical
CMOS circuit guidelines:
- Apply power supplies first (+15, -15V and ground).
- Apply digital control signals next.
- Apply analog signals last.
The reverse sequence should be followed during power down
of the circuit.
TYPICAL 16-BIT DATA WORD READ
LL, LM = No connect (Pulled Hi)
LA = Controlled
1.
2.
3.
4.
LA High for 200 nS min.
LA Lo for 200 nS min. and Hold
Data Read
LA set back Hi (for next data read repeat from Step 1.)
200 nS min.
TRANSPARENT
LATCHED
DATA 1-16 BITS
125 nS min.
With LA set Lo = 125 nS min.
With LL, LM, LA tied together = 200 nS min.
Data Changing
Data Stable
FIGURE 2A. LL, LM, AND LA TIMING DIAGRAM (16-BIT)
LA
200 nS min.
200 nS min.
200 nS min.
LM
Bits (1-8)
200 nS min.
LL
Bits (9-16)
DATA
125 nS min.
125 nS min.
125 nS min.
125 nS min.
LA, LM, LL
Transparent = Hi
Latched = Lo
Data Changing
Data Stable
FIGURE 2B. LL, LM, AND LA TIMING DIAGRAM(8-BIT)
Data Device Corporation
www.ddc-web.com
DRC-11522
R-12/06-0
5
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