SN74AHC32-EP
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS488 – JUNE 2003
D
D
D
D
D
D
D
D
D
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
†
EPIC (Enhanced-Performance Implanted
CMOS) Process
Operating Range 2-V to 5.5-V V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
The SN74AHC32 is a quadruple 2-input positive-OR gate. This device performs the Boolean function
Y
+
A
•
B or Y
+
A
)
B in positive logic.
TA
–55°C to 125°C
55°C
SOIC – D
TSSOP – PW
ORDERING INFORMATION
PACKAGE‡
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74AHC32MDREP
SN74AHC32MPWREP
TOP-SIDE
MARKING
AHC32MEP
AHC32EP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
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1
SN74AHC32-EP
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS488 – JUNE 2003
logic symbol
†
1A
1B
2A
2B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
11
4Y
8
3Y
6
2Y
≥
1
3
1Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74AHC32-EP
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS488 – JUNE 2003
recommended operating conditions (see Note 3)
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VIL
VI
VO
IOH
Low-level input voltage
Input voltage
Output voltage
High-level output current
VCC = 2 V
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 2 V
IOL
Low-level output current
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 3 V
VCC = 5.5 V
0
0
2
1.5
2.1
3.85
0.5
0.9
1.65
5.5
VCC
–50
–4
–8
50
4
8
100
20
V
V
V
V
MAX
5.5
UNIT
V
m
A
mA
m
A
mA
ns/V
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
–55
125
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = –50
m
A
VOH
IOH = –4 mA
IOH = –8 mA
IOL = 50
m
A
VOL
IOL = 4 mA
II
ICC
Ci
IOL = 8 mA
VI = 5.5 V or GND
VI = VCC or GND,
VI = VCC or GND
IO = 0
3V
4.5 V
3V
4.5 V
2V
3V
4.5 V
3V
4.5 V
0 V to 5.5 V
5.5 V
5V
2
TA = 25°C
MIN
TYP
MAX
1.9
2.9
4.4
2.58
3.94
0.1
0.1
0.1
0.36
0.36
±0.1
2
10
2
3
4.5
MIN
1.9
2.9
4.4
2.48
3.8
0.1
0.1
0.1
0.5
0.5
±1
20
V
V
MAX
UNIT
m
A
m
A
pF
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SN74AHC32-EP
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS488 – JUNE 2003
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
A or B
A or B
TO
(OUTPUT)
Y
Y
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
5.5
5.5
8
8
7.9
7.9
11.4
11.4
MIN
1
1
1
1
MAX
9.5
9.5
13
13
UNIT
ns
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
A or B
A or B
TO
(OUTPUT)
Y
Y
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
3.8
3.8
5.3
5.3
5.5
5.5
7.5
7.5
MIN
1
1
1
1
MAX
6.5
6.5
8.5
8.5
UNIT
ns
ns
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25°C (see Note 4)
PARAMETER
VOL(P)
VOL(V)
VOH(V)
VIH(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
3.5
1.5
MIN
TYP
0.3
–0.3
4.7
MAX
0.8
–0.8
UNIT
V
V
V
V
V
VIL(D)
Low-level dynamic input voltage
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
f = 1 MHz
TYP
14
UNIT
pF
4
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SN74AHC32-EP
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS488 – JUNE 2003
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
S1
VCC
Open
GND
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
VCC
Timing Input
50% VCC
tsu
Data Input
0V
50% VCC
th
0V
VCC
50% VCC
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC
50% VCC
tPZL
50% VCC
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
50% VCC
0V
tPLZ
≈V
CC
VOL + 0.3 V
tPHZ
VOH – 0.3 V
VOH
≈0
V
VOL
tw
VCC
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS
PULSE DURATION
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
50% VCC
50% VCC
0V
tPHL
Output
Control
50% VCC
VOH
50% VCC
VOL
tPLH
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
3 ns, tf
≤
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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