• Configuration options allow various multiplications of
the reference frequency—refer to
Table 1
to determine
the specific option which meets your multiplication
needs
• Available in 8-pin SOIC package
Table 1. Configuration Options
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
FS0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
OUT1
2 X REF
4 X REF
REF
8 X REF
4 X REF
8 X REF
2 X REF
16 X REF
OUT2
REF
2 X REF
REF/2
4 X REF
2 X REF
4 X REF
REF
8 X REF
Block Diagram
FBIN
External feedback connection to
OUT1 or OUT2, not both
Pin Configuration
SOIC
FBIN
IN
GND
1
2
3
4
8
7
6
5
OUT2
VDD
OUT1
FS1
FS0
FS1
÷Q
FS0
IN
Reference
Input
Phase
Detector
Charge
Pump
Loop
Filter
Output
Buffer
VCO
÷2
Output
Buffer
OUT1
OUT2
Cypress Semiconductor Corporation
Document #: 38-07154 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 29, 2005
CY2302
Pin Definitions
Pin Name
IN
FBIN
Pin No.
2
1
Pin
Type
I
I
Pin Description
Reference Input:
The output signals will be synchronized to this signal.
Feedback Input:
This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations will be synchronized to the REF signal input (IN).
Output 1:
The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see
Table 1).
Output 2:
The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See
Table 1.
Power Connections:
Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-µF
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter perfor-
mance.
Ground Connection:
Connect all grounds to the common system ground plane.
Function Select Inputs:
Tie to V
DD
(HIGH, 1) or GND (LOW, 0) as desired per
Table 1.
sheet titled “How to Implement Zero Delay,” and “Inserting
Other Devices in Feedback Path.”
The CY2302 is a pin-compatible upgrade of the Cypress
W42C70-01. The CY2302 addresses some application
dependent problems experienced by users of the older device.
OUT1
OUT2
VDD
6
8
7
O
O
P
GND
FS0:1
3
4, 5
P
I
Overview
The CY2302 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing
maximum flexibility when implementing the Zero Delay
feature. This is explained further in the sections of this data
C
A
G
Ferrite
Bead
V+
Power Supply Connection
C8
G
10 µF
0.01 µF
FBIN
IN
GND
FS0
OUT 2
1
2
3
G
8
7
6
5
V
DD
22Ω
C9 = 0.1 µF
OUTPUT 2
G
OUT 1
22Ω
OUTPUT 1
4
FS1
Figure 1. Schematic/Suggested Layout
Document #: 38-07154 Rev. *A
Page 2 of 7
CY2302
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be implemented by either
making the trace to the FBIN pin a little shorter or a little longer
than the traces to the devices being clocked.
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay from the ZDB output to the ASIC/Buffer output must be
accounted for.
Reference
Signal
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
Figure 2. Six Output Buffer in the Feedback Path
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals to the signal coming from
some other device. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) that is
put into the feedback path.
Referring to
Figure 2,
if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
Phase Alignment
In cases where OUT1 (i.e., the higher frequency output) is
connected to FBIN input pin the output OUT2 rising edges may
be either 0 or 180° phase aligned to the IN input waveform (as
set randomly when the input and/or power is supplied). If
OUT2 is desired to be rising-edge aligned to the IN input’s
rising edge, then connect the OUT2 (i.e., the lowest frequency
output) to the FBIN pin. This set-up provides a consistent
input-output phase relationship.
Document #: 38-07154 Rev. *A
Page 3 of 7
CY2302
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
.
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
P
D
Description
Voltage on Any Pin with Respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
DC Electrical Characteristics
:
T
A
= 0°C to 70°C or –40° to 85°C, V
DD
= 3.3V ±5%
Parameter
I
DD
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
I
OL
= 12 mA
I
OH
= -12 mA
V
IN
= 0V
V
IN
= V
DD
Test Condition
Unloaded, 100 MHz
Min.
—
—
2.0
—
2.4
–40
—
Typ.
17
—
—
—
—
—
—
0.4
—
5
5
Max.
35
0.8
Unit
mA
V
V
V
V
µA
µA
DC Electrical Characteristics
:
T
A
= 0°C to 70°C or –40° to 85°C, V
DD
= 5V ±10%
Parameter
I
DD
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
I
OL
= 12 mA
I
OH
= -12 mA
V
IN
= 0V
V
IN
= V
DD
Test Condition
Unloaded, 100 MHz
Min.
—
—
2.0
—
2.4
–80
Typ.
37
—
—
—
—
—
—
5
5
0.4
Max.
50
0.8
Unit
mA
V
V
V
V
µA
µA
Document #: 38-07154 Rev. *A
Page 4 of 7
CY2302
AC Electrical Characteristics:
T
A
= 0°C to +70°C or –40° to 85°C, V
DD
= 3.3V ±5%
[3]
Parameter
f
IN
f
OUT
t
R
t
F
t
ICLKR
t
ICLKF
t
D
t
LOCK
t
JC
t
DC
t
SKEW
t
PD
Description
Input Frequency
[1]
Output Frequency
Output Rise Time
Output Fall Time
Input Clock Rise
Time
[2]
Input Clock Fall Time
[2]
Duty Cycle
PLL Lock Time
Jitter, Cycle-to-Cycle
Die Out Time
[6]
Output-output Skew
[4]
Propagation Delay
[4]
15-pF load
[5]
Power supply stable
OUT1, f
OUT
>30 MHz
OUT2, f
OUT
>30 MHz
OUT1 15-pF load
0.8V to 2.0V, 15-pF load
2.0V to 0.8V, 15-pF load
Test Condition
Min.
5
10
—
—
—
—
40
—
—
—
100
—
–350
Typ.
—
—
—
—
—
—
50
—
200
90
—
65
90
Max.
133
133
3.5
2.5
10
10
60
1.0
300
300
—
250
350
Unit
MHz
MHz
ns
ns
ns
ns
%
ms
ps
ps
Clock Cycles
ps
ps
AC Electrical Characteristics:
T
A
= 0°C to +70°C or –40° to 85°C, V
DD
= 5.0V ±10%
[3]
Parameter
f
IN
f
OUT
t
R
t
F
t
ICLKR
t
ICLKF
t
D
t
LOCK
t
JC
t
DC
t
SKEW
t
PD
Description
Input Frequency
[1]
Output Frequency
Output Rise Time
Output Fall Time
Input Clock Rise Time
[2]
Input Clock Fall Time
[2]
Duty Cycle
PLL Lock Time
Jitter, Cycle-to-Cycle
Die out time
[6]
Output-output Skew
[4]
Propagation Delay
[4]
15-pF load
[5, 7]
Power supply stable
OUT1, f
OUT
>30 MHz
OUT2, f
OUT
>30 MHz
OUT1 15-pF load
0.8V to 2.0V, 15-pF load
2.0V to 0.8V, 15-pF load
Test Condition
Min.
5
10
—
—
—
—
40
—
—
—
100
—
–350
—
—
—
—
—
50
—
200
90
—
65
90
Typ.
Max.
133
133
2.5
1.5
10
10
60
1.0
300
300
—
250
350
Unit
MHz
MHz
ns
ns
ns
ns
%
ms
ps
ps
clock
cycles
ps
ps
Notes:
1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2. Longer input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
4. Skew is measured at 1.4V on rising edges.
5. Duty cycle is measured at 1.4V.
6. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to <16 MHz.
7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.
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